ModuleWare Reference Guide - Hornad

Register PartsD Flip-Flop (adff)D Flip-Flop (adff)This part is a highly parameterized D-type flip-flop. Upon a trigger of anenabled scalar input port clk, the data from the input port d is propagatedinto the output ports q and qb.The optional output port qb has a bitwise inverted value of the output portq and can be enabled by setting the enumerated parameter qb_type(Enabled, Disabled). Note that using qb does not imply extra inverters,these inverters are usually absorbed by inferred flip-flops because mosthave a qb port.The part can be triggered on the rising or the falling edge of the scalar input port clk. Thepolarity of clk is controlled by the enumerated parameter clk_type (Rising, Falling, RisingLast,FallingLast, RisingEdge, FallingEdge) where RisingLast, FallingLast, RisingEdge, FallingEdgeare supported for VHDL only.The flip-flop has a scalar input port load with its mode controlled by the enumerated parameterload_type (ActiveHigh, ActiveLow, None).The register can be set or reset to the value of the parameter set_val and rst_val by activating thescalar input ports set and rst. The modes for these inputs are controlled by enumeratedparameters set_type and rst_type (AsyncActiveHigh, SyncActiveHigh, AsyncActiveLow,SyncActiveLow, None). If the mode for these inputs is set to None or if they are unconnected,then the respective pins are not visible in the symbol and the functionality for that pin isdisabled. The modes for these ports can be synchronous or asynchronous.The enumerated parameter initialization (Enabled, Disabled) determines whether the localregisters have an initial value.This part is equivalent to n flip-flops, where n is the width of the ports d, q and qb. The inferredregister depends upon the type of rst and set behavior. The gate count greatly changes if thesynthesis tool is able to pick up smaller flip-flops.If set, rst or load are not connected, the code for unused ports is removed.Parameters set_val and rst_val can take LNBF format as described in the Constant Value(constval) model, with no limitation on the size of the q and qb ports.FunctionIf rst and set are synchronous, then at every clk trigger (rising edge if clk_type = Rising; fallingedge if clk_type = Falling):qqb= rst_val= set_val= d= NOT(rst_val)= NOT(set_val)= NOT(d)if rst is activeIf set is activeIf load is active or not connectedIf rst is activeIf set is activeIf load is active or not connected140ModuleWare Reference Manual, Library Version 1.9September 18, 2008