ModuleWare Reference Guide - Hornad

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List of TablesTable 2-40. Variable Width N-Input OR Gate Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 2-41. Variable Width N-Input OR Gate Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 2-42. Variable Width N-Input XOR Gate Truth Table . . . . . . . . . . . . . . . . . . . . . . . . 58Table 2-43. Variable Width N-Input XOR Gate Parameters . . . . . . . . . . . . . . . . . . . . . . . . 58Table 3-1. Constant Value Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 3-2. Ground Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 3-3. Power Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 4-1. Decoder Truth Table — Two Separate Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 4-2. Decoder Truth Table — Four Separate Outputs . . . . . . . . . . . . . . . . . . . . . . . . . 65Table 4-3. Decoder Truth Table — Eight Separate Outputs . . . . . . . . . . . . . . . . . . . . . . . . 65Table 4-4. Decoder Parameters — Separate Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66Table 4-5. Decoder Truth Table — Combined Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67Table 4-6. Decoder Parameters — Combined Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68Table 4-7. Encoder Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69Table 4-8. Encoder Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 4-9. N-Input Multiplexer Truth Table — Two Inputs . . . . . . . . . . . . . . . . . . . . . . . . 72Table 4-10. N-Input Multiplexer Truth Table — Four Inputs . . . . . . . . . . . . . . . . . . . . . . . 72Table 4-11. N-Input Multiplexer Truth Table — Eight Inputs . . . . . . . . . . . . . . . . . . . . . . . 72Table 4-12. N-Input Multiplexer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 4-13. N-Input One-hot Multiplexer Truth Table — Priority Enabled, Two-Input . . . 75Table 4-14. N-Input One-hot Multiplexer Truth Table — Priority Enabled, Four-Input . . . 75Table 4-15. N-Input One-hot Multiplexer Truth Table — Priority Enabled, Eight-Input . . 75Table 4-16. N-Input One-hot Multiplexer Truth Table — Priority Disabled, Two-Input . . 76Table 4-17. N-Input One-hot Multiplexer Truth Table — Priority Disabled, Four-Input . . 76Table 4-18. N-Input One-hot Multiplexer Truth Table — Priority Disabled, Eight-Input . . 76Table 4-19. N-Input One-hot Multiplexer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Table 4-20. W-Bit Multiplexer Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 4-21. W-Bit Multiplexer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 5-1. N-Bus Merge Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Table 5-2. N-Bus Merge Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Table 5-3. N-Bus Merge Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 5-4. N-Bus Merge Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 5-5. N-Bus Merge Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 5-6. N-Bus Merge Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 5-7. N-Bus Merge Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 5-8. N-Bus Merge Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 5-9. N-Bus Merge Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 5-10. N-Bus Merge Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Table 5-11. N-Way Splitter Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 5-12. N-Way Splitter Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 5-13. N-Way Splitter Truth Table — Two-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 5-14. N-Way Splitter Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 5-15. N-Way Splitter Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 5-16. N-Way Splitter Truth Table — Four-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Table 5-17. N-Way Splitter Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 888ModuleWare Reference ManualSeptember 18, 2008
List of TablesTable 5-18. N-Way Splitter Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 5-19. N-Way Splitter Truth Table — Eight-Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 5-20. N-Way Splitter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 5-21. Bus Fill Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 5-22. Bus Fill Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 5-23. Bus Trapper Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 5-24. Bus Trapper Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 5-25. Fixed Bit Selector Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 5-26. Fixed Bit Selector Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 5-27. Fixed Bit Setter Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 5-28. Fixed Bit Setter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 5-29. Fixed Shifter Truth Table — Mode = Logical . . . . . . . . . . . . . . . . . . . . . . . . . 94Table 5-30. Fixed Shifter Truth Table — Mode = Arithmetic . . . . . . . . . . . . . . . . . . . . . . . 95Table 5-31. Fixed Shifter Truth Table — Mode = Circular . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 5-32. Fixed Shifter Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 6-1. 181 ALU Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Table 6-2. 181 ALU Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Table 6-3. Absolute Value Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Table 6-4. Absolute Value Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Table 6-5. Accumulator Truth Table — Asynchronous high rst, Positive Polarities . . . . . . 104Table 6-6. Accumulator Truth Table — Synchronous high rst, Positive Polarities . . . . . . . 105Table 6-7. Accumulator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Table 6-8. Adder Truth Table — Unsigned, 3-bit din0, din1 and dout . . . . . . . . . . . . . . . . 106Table 6-9. Adder Truth Table — Unsigned, 3-bit din0, 4-bit din1, 4-bit dout . . . . . . . . . . . 107Table 6-10. Adder Truth Table — Unsigned, 3-bit din0, 4-bit din1, 5-bit dout . . . . . . . . . . 107Table 6-11. Adder Truth Table — Signed, 3-bit din0, din1 and dout . . . . . . . . . . . . . . . . . 107Table 6-12. Adder Truth Table — Signed, 3-bit din0, 4-bit din1, 4-bit dout . . . . . . . . . . . . 108Table 6-13. Adder Truth Table — Signed, 3-bit din0, 4-bit din1, 5-bit dout . . . . . . . . . . . . 108Table 6-14. Adder Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109Table 6-15. Adder Subtractor Truth Table — Three-bit, Unsigned, Positive Polarities, cin=0110Table 6-16. Adder Subtractor Truth Table — Three-bit, Signed, cin=0 . . . . . . . . . . . . . . . 111Table 6-17. Adder Subtractor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Table 6-18. Bit Tally Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Table 6-19. Bit Tally Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113Table 6-20. Comparator Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Table 6-21. Comparator Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Table 6-22. Decrementer Truth Table — 3-bit, Unsigned, Positive Polarities . . . . . . . . . . . 116Table 6-23. Decrementer Truth Table — 3-bit, Signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Table 6-24. Decrementer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Table 6-25. Incrementer Truth Table — 3-bit, Unsigned, Positive Polarities . . . . . . . . . . . 118Table 6-26. Incrementer Truth Table — 3-bit, Signed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Table 6-27. Incrementer Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Table 6-28. Incrementer Decrementer Truth Table — 3-bit, Unsigned, Positive Polarities 120Table 6-29. Incrementer Decrementer Truth Table — 3-bit, Signed . . . . . . . . . . . . . . . . . . 121ModuleWare Reference Manual 9September 18, 2008
Page 1: ModuleWare Reference Manualfor the
Page 4 and 5: Table of ContentsGated OR (or1) . .
Page 6: Table of ContentsBufif0 Primitive (
Page 11 and 12: List of TablesTable 7-20. RS Flip-F
Page 14 and 15: List of TablesTable 10-41. XNOR Pri
Page 16 and 17: IntroductionNaming ConventionsNamin
Page 18 and 19: IntroductionSupported VHDL Packages
Page 20 and 21: IntroductionReset/Clear BehaviorYou
Page 22 and 23: IntroductionSet/Preset BehaviorSet/
Page 24 and 25: IntroductionGate BehaviorFunctioncl
Page 26 and 27: IntroductionEnable/Load BehaviorFun
Page 28 and 29: IntroductionVHDL Coding StyleNotes
Page 30 and 31: IntroductionDesign Rule CheckingFor
Page 32 and 33: IntroductionSlice SupportOtherwise
Page 34 and 35: Logic PartsN-Input AND Gate (and)N-
Page 36 and 37: Logic PartsN-Input XOR Gate (xor)N-
Page 38 and 39: Logic PartsN-Input NOR Gate (nor)N-
Page 40 and 41: Logic PartsAssign (assignment)Assig
Page 42 and 43: Logic PartsBit Setter (bitset)suffi
Page 44 and 45: Logic PartsBus Driver (busdrive)Bus
Page 46 and 47: Logic PartsGated OR (or1)Gated OR (
Page 48 and 49: Logic PartsInverter (inv)Inverter (
Page 50 and 51: Logic PartsReduction OR (tor)Reduct
Page 52 and 53: Logic PartsThree-state Buffer (trib
Page 54 and 55: Logic PartsThree-state bus (tribus)
Page 56 and 57: Logic PartsVariable Width N-Input A
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Logic PartsVariable Width N-Input X
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ConstantsConstant Value (constval)C
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ConstantsPower (vdd)Power (vdd)This
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Combine
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Combinatorial PartsEncoder (encoder
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Combinatorial PartsN-Input Multiple
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsW-Bit Multiplexe
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Combinatorial PartsW-Bit Multiplexe
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsBus Fill (wor
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Bit Manipulation PartsFixed Bit Sel
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Bit Manipulation PartsFixed Shifter
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Bit Manipulation PartsFixed Shifter
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Arithmetic Parts181 ALU (alu181)181
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Arithmetic Parts181 ALU (alu181)ovf
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Arithmetic PartsAbsolute Value (abs
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Arithmetic PartsAccumulator (acc)ad
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Arithmetic PartsAdder (add)Adder (a
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Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
Page 116 and 117:
Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
Page 122 and 123:
Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
Page 150 and 151:
Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Latches (la
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Sequential PartsClock Divider (clkd
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Sequential PartsConfigurable Counte
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Page 182 and 183:
Page 184 and 185:
Page 186 and 187:
Page 188 and 189:
Page 190 and 191:
Sequential PartsModulo Counter (mod
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Page 194 and 195:
Page 196 and 197:
Sequential PartsParallel to Serial
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Sequential PartsParallel to Serial
Page 200 and 201:
Sequential PartsSerial to Parallel
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Sequential PartsThree-state Bank of
Page 204 and 205:
Sequential PartsThree-state Bank of
Page 206 and 207:
Memory PartsDual Port RAM (ram2p)Du
Page 208 and 209:
Memory PartsFirst In First Out (fif
Page 210 and 211:
Memory PartsFirst In First Out (fif
Page 212 and 213:
Memory PartsSingle Port RAM (ram)Si
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Memory PartsRegister File (regfile)
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Memory PartsROM (rom)ROM (rom)This
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Memory PartsROM (rom)The correspond
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Memory PartsROM (rom)Extended segme
Page 222 and 223:
Memory PartsStack (stack)The reset
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Memory PartsStack (stack)Parameters
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Memory PartsSynthesizable Dual-Port
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Memory PartsSynthesizable Single-Po
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Primitive PartsIntroductionIntroduc
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Primitive PartsIntroductionTable 10
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Primitive PartsBuffer Primitive (pb
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Primitive PartsBufif0 Primitive (pb
Page 238 and 239:
Primitive PartsBufif1 Primitive (pb
Page 240 and 241:
Primitive PartsCMOS Primitive (pcmo
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Primitive PartsNAND Primitive (pnan
Page 244 and 245:
Primitive PartsNOR Primitive (pnor)
Page 246 and 247:
Primitive PartsNOT Primitive (pnot)
Page 248 and 249:
Primitive PartsNotif0 Primitive (pn
Page 250 and 251:
Primitive PartsNotif1 Primitive (pn
Page 252 and 253:
Primitive PartsPMOS Primitive (ppmo
Page 254 and 255:
Primitive PartsPullup Primitive (pp
Page 256 and 257:
Primitive PartsRCMOS Primitive (prc
Page 258 and 259:
Primitive PartsRPMOS Primitive (prp
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Primitive PartsXNOR Primitive (pxno
Page 262 and 263:
Stimulus PartsSimple Clock (clk)Sim
Page 264 and 265:
Stimulus PartsCompound Clock (cmpdc
Page 266 and 267:
Stimulus PartsPulse (pulse)Pulse (p
Page 268 and 269:
Stimulus PartsConstant Wave (constw
Page 270 and 271:
Stimulus PartsRandom Value (random)
Page 272 and 273:
Stimulus PartsRandom Value (random)
Page 274 and 275:
Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
Page 294:
15. CONTROLLING LAW, JURISDICTION A
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