ModuleWare Reference Guide - Hornad

Sequential PartsClock Divider (clkdiv)ParametersTable 8-8. Clock Divider ParametersParameter Values Defaultclk_en_typeclk_typerst_typedivide_byduty_cycleActiveHigh,ActiveLow,NoneRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeSyncActiveHigh,AsyncActiveHigh,SyncActiveLow,AsyncActiveLowDivider valueLocation of the output rising edgeActiveHighRisingAsyncActiveHigh21Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, clk_en,clk_out and rst do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports rst, clk andclk_out are not connected.ModuleWare Reference Manual, Library Version 1.9 177September 18, 2008