ModuleWare Reference Guide - Hornad

A BC D E F G H I J K L M N O P Q R S T U V W XY Zpnotif1, 249por, 251Portclock, 23clock enable, 25dynamic, 31enable/load, 26gate, 24mixed types, 31naming and location, 16polarity control, 18reset, 19reset/clear, 20set/preset, 22slice width, 32width, 31Power, 62ppmos, 252ppulldown, 253ppullup, 254prcmos, 255Preferenceblocking or non-blocking assignments, 29signal name prefix in generated HDL, 29use signal names in generated VHDL, 28VHDL coding style, 28prnmos, 257prpmos, 258Pulldown Primitive, 253Pullup Primitive, 254Pulse, 266pulse, 266pxnor, 260pxor, 259— R —RAM, 206ram, 212ram2p, 206ramdp, 225ramsp, 227random, 270Random Value, 270RCMOS Primitive, 255Reduction AND, 49Reduction OR, 50Reduction XOR, 51regfile, 214Register File, 214ResetAsyncActiveHigh, 19AsyncActiveLow, 19SyncActiveHigh, 19SyncActiveLow, 19Reset/Clear Behavior, 20Right Shifter, 128RNMOS Primitive, 257ROM, 216rom, 216RPMOS Primitive, 258RS Flip-Flop, 154RS Latch, 157rsff, 154rshift, 128rslatch, 157— S —sand, 56Serial to Parallel Shifter, 199Shiftermodes, 27shiftps, 195shiftsp, 199Simple Clock, 262Single Port RAM, 212sor, 57split, 86Stack, 221stack, 221sub, 130Subtractor, 130sxor, 58Synthesizable Dual-Port RAM, 225Synthesizable Single-Port RAM, 227— T —T Flip-Flop, 161T Latch, 164tally, 113tand, 49tap, 91tff, 161ModuleWare Reference Manual, Library Version 1.9September 18, 2008289