ModuleWare Reference Guide - Hornad

Memory PartsSingle Port RAM (ram)Single Port RAM (ram)This part implements a Random Access Memory (RAM). The depthof the RAM is given by the parameter ram_size. The internal memoryelements have a latch behavior (that is, they are level sensitive).The RAM has write and read operations. The write operation takesplace if the scalar input port oena is enabled (oena = 1). The readoperation takes place if the scalar input port iena is enabled (iena =1).In a write operation, the value of the input bus din is written to theaddress location specified by the value of the input bus addr.In a read operation, the value in the address location specified by addr is placed on the outputport dout. If the write operation is disabled, the output port dout goes to tristate mode.Even though read and write operations can be done simultaneously, it is not recommended.Because only one memory address can be accessed at any given time, a simultaneous operationmeans read and write to the same location.An internal RAM table is maintained. When write is not taking place, this table maintains itsvalue. If the value of the address port is greater than the value of ram_size, the scalar output portaddr_error is set to 1. In such cases, read or write operations do not take place. The RAMoperations are disabled if the address is out of range.The part has no timing control. Users are responsible for the timing control and to verify that thevalues on the input ports are retained for sufficient time. You need a good sequential memorycontroller for this part to work in a sequential design. We recommend that you do not synthesizethis part, because memory compilers perform much better than logic synthesis on memory parts.This is a non-synthesizable part. Even though synthesis tools can accept the code generated forthis part, you are advised not to synthesize this part.Functionram_table is a table of internal locations. The number of locations are given by the parameterram_size:ram_table(addr) = din if iena = 1. and addr < ram_sizedout= ram_table(addr) if oena = 1 and addr < ram_size= ZZ...otherwiseaddr_error = 0= 1if addr < ram_sizeotherwise212ModuleWare Reference Manual, Library Version 1.9September 18, 2008