ModuleWare Reference Guide - Hornad

Sequential PartsClock Divider (clkdiv)Functioninternalregthe internal register.If reset is synchronous, then at every enabled clk trigger (rising edge if clk_type = Rising;falling edge if clk_type = Falling):internalreg = 0= 0= internalreg +1if rst is activeif internalreg >= (divide_by - 1)otherwiseIf reset is asynchronous (rst_type = AsyncActiveHigh, or rst_type = AsyncActiveLow):internalreg = 0 if rst is active (irrespective of the clk trigger), elseat every enabled clk trigger (rising edge if clk_type = Rising; falling edge if clk_type = Falling):internalreg = 0= internalreg +1Truth Tableif internalreg >= (divide_by - 1), elseotherwiseclk_out = internalreg > = (divide_by - duty_cycle)creginternal register.The following tables are for positive polarities. For negative polarities, invert the values.This table is for asynchronous high reset and positive polarities:Table 8-6. Clock Divider Truth Table — Asynchronous High Reset, PositivePolaritiesclk_en clk rst creg- - 1 00 - 0 creg1 Posedge 0 if (creg >= divide_by - 1) = 0; else creg+1This table is for synchronous high reset and positive polarities:Table 8-7. Clock Divider Truth Table — Synchronous High Reset, PositivePolaritiesclk_en clk rst creg0 - - creg1 Posedge 1 01 Posedge 0 if (creg >= divide_by - 1) = 0; else creg+1clk_out = creg >= (divide_by - duty_cycle)176ModuleWare Reference Manual, Library Version 1.9September 18, 2008