ModuleWare Reference Guide - Hornad

Register PartsD Latch (dlatch)Table 7-7. D Latch Truth Table — Synchronous rst and set, Asynchronousload (cont.)load gate rst set q qbNC 1 0 / NC 0 / NC d NOT(d)0 1 0 / NC 0 / NC q qb1 1 0 / NC 0 / NC d NOT(d)ParametersTable 7-8. D Latch ParametersParameter Values Defaultd, q, qb Port widths (must be > 0) Automaticgate_typeload_typeqb_typerst_typeset_typeinitializationrst_valset_valActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister reset value (must be >= 0)Register set value (must be >= 0)ActiveHighSyncActiveHighEnabledAsyncActiveHighAsyncActiveHighDisabled01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, load, rst, andset do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if either ports d and clk are notconnected or if at least one of ports q and qb are not connected.146ModuleWare Reference Manual, Library Version 1.9September 18, 2008