ModuleWare Reference Guide - Hornad

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Bit Manipulation PartsN-Bus Merge (merge)Truth Table (8-Bus examples)Example merging six 2-bit buses (din7 to din2) and two 1-bit buses (din1 and din0) into a 14-bit output bus (dout):Table 5-7. N-Bus Merge Truth Table — Eight-Busdin7 din6 din5 din4 din3 din2 din1 din0 dout00 01 10 00 00 10 0 0 0001100000100000 10 11 11 11 11 1 0 0010111111111001 01 00 10 01 00 0 0 0101001001000010 11 01 11 00 01 0 1 10110111000101Example merging six 2-bit buses (din7 to din2) and two 1-bit buses (din1 and din0) into a 15-bit output bus (dout) showing how the undefined bit in dout is filled with an X:Table 5-8. N-Bus Merge Truth Table — Eight-Busdin7 din6 din5 din4 din3 din2 din1 din0 dout00 01 10 00 00 10 0 0 X0001100000100000 10 11 11 11 11 1 0 X0010111111111001 01 00 10 01 00 0 0 X0101001001000010 11 01 11 00 01 0 1 X10110111000101Example merging six 2-bit buses (din7 to din2) and two 1-bit buses (din1 and din0) into a 10-bit output bus (dout) discarding the bits in din6 and din7:Table 5-9. N-Bus Merge Truth Table — Eight-Busdin7 din6 din5 din4 din3 din2 din1 din0 dout00 01 10 00 00 10 0 0 100000100000 10 11 11 11 11 1 0 111111111001 01 00 10 01 00 0 0 1001001000010 11 01 11 00 01 0 1 011100010184ModuleWare Reference Manual, Library Version 1.9September 18, 2008
Bit Manipulation PartsN-Bus Merge (merge)ParametersTable 5-10. N-Bus Merge ParametersParameters Values Defaultdin0 to dinN, dout Port width (must be > 0) AutomaticDesign Rule Checks• An error is issued if the width of any port cannot be determined.• A warning is issued and HDL generation fails for this part if any ports are not connected.ModuleWare Reference Manual, Library Version 1.9 85September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
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List of TablesTable 5-18. N-Way Spl
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List of TablesTable 7-20. RS Flip-F
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List of TablesTable 10-41. XNOR Pri
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IntroductionNaming ConventionsNamin
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IntroductionSupported VHDL Packages
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IntroductionReset/Clear BehaviorYou
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IntroductionSet/Preset BehaviorSet/
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IntroductionGate BehaviorFunctioncl
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IntroductionEnable/Load BehaviorFun
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IntroductionVHDL Coding StyleNotes
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IntroductionDesign Rule CheckingFor
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IntroductionSlice SupportOtherwise
Page 34 and 35: Logic PartsN-Input AND Gate (and)N-
Page 36 and 37: Logic PartsN-Input XOR Gate (xor)N-
Page 38 and 39: Logic PartsN-Input NOR Gate (nor)N-
Page 40 and 41: Logic PartsAssign (assignment)Assig
Page 42 and 43: Logic PartsBit Setter (bitset)suffi
Page 44 and 45: Logic PartsBus Driver (busdrive)Bus
Page 46 and 47: Logic PartsGated OR (or1)Gated OR (
Page 48 and 49: Logic PartsInverter (inv)Inverter (
Page 50 and 51: Logic PartsReduction OR (tor)Reduct
Page 52 and 53: Logic PartsThree-state Buffer (trib
Page 54 and 55: Logic PartsThree-state bus (tribus)
Page 56 and 57: Logic PartsVariable Width N-Input A
Page 58 and 59: Logic PartsVariable Width N-Input X
Page 60 and 61: ConstantsConstant Value (constval)C
Page 62 and 63: ConstantsPower (vdd)Power (vdd)This
Page 64 and 65: Combinatorial PartsDecoder, Separat
Page 66 and 67: Combinatorial PartsDecoder, Separat
Page 68 and 69: Combinatorial PartsDecoder, Combine
Page 70 and 71: Combinatorial PartsEncoder (encoder
Page 72 and 73: Combinatorial PartsN-Input Multiple
Page 74 and 75: Combinatorial PartsN-Input One-hot
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Page 78 and 79: Combinatorial PartsW-Bit Multiplexe
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Page 82 and 83: Bit Manipulation PartsN-Bus Merge (
Page 86 and 87: Bit Manipulation PartsN-Way Splitte
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Page 90 and 91: Bit Manipulation PartsBus Fill (wor
Page 92 and 93: Bit Manipulation PartsFixed Bit Sel
Page 94 and 95: Bit Manipulation PartsFixed Shifter
Page 96 and 97: Bit Manipulation PartsFixed Shifter
Page 98 and 99: Arithmetic Parts181 ALU (alu181)181
Page 100 and 101: Arithmetic Parts181 ALU (alu181)ovf
Page 102 and 103: Arithmetic PartsAbsolute Value (abs
Page 104 and 105: Arithmetic PartsAccumulator (acc)ad
Page 106 and 107: Arithmetic PartsAdder (add)Adder (a
Page 108 and 109: Arithmetic PartsAdder (add)Table 6-
Page 110 and 111: Arithmetic PartsAdder Subtractor (a
Page 112 and 113: Arithmetic PartsAdder Subtractor (a
Page 114 and 115: Arithmetic PartsComparator (cmp)Com
Page 116 and 117: Arithmetic PartsDecrementer (dec)De
Page 118 and 119: Arithmetic PartsIncrementer (inc)In
Page 120 and 121: Arithmetic PartsIncrementer Decreme
Page 122 and 123: Arithmetic PartsIncrementer Decreme
Page 124 and 125: Arithmetic PartsLeft Shifter (lshif
Page 126 and 127: Arithmetic PartsMultiplier (mult)A
Page 128 and 129: Arithmetic PartsRight Shifter (rshi
Page 130 and 131: Arithmetic PartsSubtractor (sub)Sub
Page 132 and 133: Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Latches (la
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Sequential PartsClock Divider (clkd
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Sequential PartsConfigurable Counte
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Sequential PartsModulo Counter (mod
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Sequential PartsParallel to Serial
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Sequential PartsParallel to Serial
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Sequential PartsSerial to Parallel
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Sequential PartsThree-state Bank of
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Sequential PartsThree-state Bank of
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Memory PartsDual Port RAM (ram2p)Du
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Memory PartsFirst In First Out (fif
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Memory PartsFirst In First Out (fif
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Memory PartsSingle Port RAM (ram)Si
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Memory PartsRegister File (regfile)
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Memory PartsROM (rom)ROM (rom)This
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Memory PartsROM (rom)The correspond
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Memory PartsROM (rom)Extended segme
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Memory PartsStack (stack)The reset
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Memory PartsStack (stack)Parameters
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Memory PartsSynthesizable Dual-Port
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Memory PartsSynthesizable Single-Po
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Primitive PartsIntroductionIntroduc
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Primitive PartsIntroductionTable 10
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Primitive PartsBuffer Primitive (pb
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Primitive PartsBufif0 Primitive (pb
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Primitive PartsBufif1 Primitive (pb
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Primitive PartsCMOS Primitive (pcmo
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Primitive PartsNAND Primitive (pnan
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Primitive PartsNOR Primitive (pnor)
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Primitive PartsNOT Primitive (pnot)
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Primitive PartsNotif0 Primitive (pn
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Primitive PartsNotif1 Primitive (pn
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Primitive PartsPMOS Primitive (ppmo
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Primitive PartsPullup Primitive (pp
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Primitive PartsRCMOS Primitive (prc
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Primitive PartsRPMOS Primitive (prp
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Primitive PartsXNOR Primitive (pxno
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Stimulus PartsSimple Clock (clk)Sim
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Stimulus PartsCompound Clock (cmpdc
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Stimulus PartsPulse (pulse)Pulse (p
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Stimulus PartsConstant Wave (constw
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Stimulus PartsRandom Value (random)
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Stimulus PartsRandom Value (random)
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Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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ModuleWare Reference Guide - Hornad

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