ModuleWare Reference Guide - Hornad

Primitive PartsIntroductionIntroductionDesigns at the logic level of abstraction describe a digital circuit in terms of primitive logicfunctions such as AND, NAND and OR etc. They allow for the nets interconnecting the logicfunctions to carry 0, 1, X and Z values.The switch level of modelling provides a level of abstraction between the logic and analogtransistorlevel of abstraction which describes the interconnection of transmission gates (whichare abstractions of individual MOS and CMOS transistors). The switch level transistors aremodelled as being either on or off, conducting or not conducting, respectively.The values carried by the interconnections are abstracted from the whole range of analogvoltages or currents to a small number of discrete values. These values are referred to as signalstrengths.Switch level modelling allows for the strength of a driving gate and the size of the capacitorstoring charge on a tri-stated register net to be modelled. This capability provides for moreaccurate simulation of the electrical properties of the transistors than would a logic simulation.The primitives are supported in both Verilog and VHDL. In VHDL, the primitives are simulatedin order to provide all the same functionality which they provide in Verilog. Hence, the codegeneration becomes slightly lengthy and complex. The following description is mainly based onthe behavior and modelling done in Verilog for the primitives and explains their simulatedbehavior in VHDL to some extent.A gate or switch declaration names a gate or switch type as well as specifying its output signalstrengths and delays. It contains one or more gate instances. Gate instances include an instancename and a required terminal connection list. The terminal connection list specifies how thegate or switch connects to other components in the part. All the instances contained in a gate orswitch declaration have the same output strengths and delays.The drive strength specifications specify the strengths of the values on the output terminals ofthe instances in the gate declaration. Strengths are supported for the logic levels, 0 and 1. Thestrength specification for the logic 0 is controlled by an enumerated parameter calledstrength0_type and similarly by strength1_type for logic 1.It is possible to specify the strength of the output signals for the following gate primitives:Gate types that support driving strengthsandnandornorbufnotnotif0notif1xorxnorbufif0bufif1pulluppulldownAs stated earlier, the drive strength specification has two parts. A gate declaration must containboth the parts, or should contain no parts, with the exception of pullup and pulldown sources.One of the parts specifies the strength of a signal with a value of 1 and the other specifies thestrength of a signal with a value of 0.230ModuleWare Reference Manual, Library Version 1.9September 18, 2008