ModuleWare Reference Guide - Hornad

IntroductionGate BehaviorFunctionclk_type = Risingclk_type = Fallingclk_type = RisingLastclk_type = FallingLastclk_type = RisingEdgeclk_type = FallingEdgerising edge event, positive polarityfalling edge event, negative polarity ( )rising edge event, last value low, positivefalling edge event, last value high, negative polarity ( )rising edge, positive polarityfalling edge, negative polarity ( )These functions correspond to the following VHDL code:RisingFallingRisingLastFallingLastRisingEdgeFallingEdgeIf (clk’EVENT AND clk='1')If (clk’EVENT AND clk='0')If (clk’EVENT AND clk='1' AND clk’LAST_VALUE='0')If (clk’EVENT AND clk='0' AND clk’LAST_VALUE='1')If (RISING_EDGE(clk))If (FALLING_EDGE(clk))Notes• The default value for the parameter clk_type is Rising.• The clk input port is always on the lower part of the left of the symbol and has a clock portindicator .Gate BehaviorAll the latches in the Register parts category have a gate port named gate. The sequentialbehavior could be triggered on the high level of the gate or the low level of the gate. Thebehavior of the gate port is controlled by the gate_type parameter.For all the parts with a gate port, the parameter gate_type is enumerated with values ActiveHighand ActiveLow. If gate_type is ActiveHigh, the part gets triggered on the high level of the gateport. If gate_type is ActiveLow, the part gets triggered on the low level of the gate port.The polarity indication ( or no or hidden) for the gate port is dynamically set by theparameter gate_type. If the value is set to ActiveLow, then an inverted signal indicator appearson the port. If the value is set to ActiveHigh, the indicator disappears.You are advised not to edit the value of the parameter gate_type if port gate is not connectedbecause this can modify the default operation. The polarity of the gate port is implemented inthe generated HDL code.24ModuleWare Reference Manual, Library Version 1.9September 18, 2008