ModuleWare Reference Guide - Hornad

Memory PartsROM (rom)ROM (rom)This part implements a synthesizable Read Only Memory (ROM)generator which reads an initialization file during HDL generation.The generator supports Intel HEX file format.The part can be triggered on either the rising edge or the falling edgeof the scalar input port clk. The polarity of clk is controlled by theenumerated parameter clk_type (Rising, Falling, RisingLast,FallingLast, RisingEdge, FallingEdge). Note that RisingLast, FallingLast, RisingEdge andFallingEdge are supported for VHDL only.The ROM is inferred by creating a ROM table. The generated HDL uses a CASE statement toinitialize the contents of the ROM table. This implementation is efficient when there aremultiple extended linear addressing records with empty locations. Empty locations need not beexplicitly addressed but are handled by the default branch of the CASE statement. This part canbe synthesized using Altera or Xilinx technologies.The ROM table is initialized based on the values in a file. The pathname of this file is given bythe parameter rom_file. The file must be in Intel HEX format.Each Intel Hex record comprises five fields (data length, address, type, data, and checksum) asdescribed in the Hexadecimal File Format (Intel Hex) section.The Intel HEX file format only supports byte-addressing, so the width of the dout port must beexactly 8 bits. The width of the addr port should be 16 bits (if the HEX file contains noextended linear addressing) or 31 bits (if the HEX file contains extended linear address records).If the address port width is less than these values, the ROM table may be reduced compared tothe number of records in the HEX file. In this case, a warning is issued but does not stop HDLgeneration.Although the HEX file can support a maximum of 32 bits of address (using extended linearaddressing) the ROM generator only supports address widths of a maximum 31 bits because anaddress width of 32 bits would make the ROM table array exceeds the maximum level whichthe array can represent.Note that extended segment addressing (record type 02) is not supported.The size of the ROM table is determined by the number of address locations inside the IntelHEX file. For example, if the address port width is 16 bits, the ROM table size will be 65535.Only the ROM table locations with corresponding addresses and data in the HEX file areaddressed.216ModuleWare Reference Manual, Library Version 1.9September 18, 2008