ModuleWare Reference Guide - Hornad

Memory PartsFirst In First Out (fifo)First In First Out (fifo)This part implements a First-In-First-Out (FIFO) queue. Data can beloaded into the internal registers and read at a later time. All theoperations in this part (except for reset) are synchronous with respectto the clock. The depth is controlled by the parameter fifo_size.The FIFO supports two input/output operations. A write operationtakes the value of the input port ffin and places it in the internalregisters. A read operation takes the oldest value in the internalregisters and places it in the output port ffout. This value is retainedon ffout until the next read operation.The read operation is controlled by the scalar input port rena and thewrite operation is controlled by the scalar input port wena. The writeoperation has precedence over the read operation. The polarity ofrena is controlled by the enumerated parameter rena_type(ActiveHigh, ActiveLow). The polarity of the scalar output port wena is controlled by theenumerated parameter wena_type (ActiveHigh, ActiveLow).The part consists of the required number of the internal registers, an address counter and thecontrol logic. Internally, the FIFO will be of depth fifo_size + 1. The extra register is used toretain the old value. It is used for driving the output port and is not a part of the FIFO memory.The address counter keeps the count of the current address. This value is used for the read andwrite operations. This counter decides whether the FIFO is empty (counter = 0) or full (counter= fifo_size). The reset operation is required before a correct operation of the FIFO (for postsynthesis simulation match). Read operations cannot be done before a write operation.Write operations are disabled if the internal registers are full (address counter = fifo_size). Readoperations are disabled if the internal registers are empty (address counter = 0). If the internalregisters are full and both write and read operations are triggered, the read operation takes placebecause the write operation is disabled. When the internal registers are full the read operationtakes precedence over the write (because write is disabled).The scalar output port full is activated if the internal registers are full. The scalar output portempty is activated if the internal registers are empty. The polarity of the scalar output port fullis controlled by the parameter full_type (ActiveHigh, ActiveLow). The polarity of the scalaroutput port empty is controlled by the parameter empty_type (ActiveHigh, ActiveLow).The part also has two ports (afull and aempty) which are used to signal an “almost-full” and“almost-empty” conditions. The polarity of these ports is controlled by the enumeratedparameters afull_type (ActiveHigh, ActiveLow) and aempty_type (ActiveHigh, ActiveLow).The almost-full and almost-empty criteria are set using the integer parameters afull_size andaempty_size.The afull port will then be asserted whenever the address counter equals or exceeds afull_size.If the parameter afull_size is less than or equal to zero (zero is also the default value forafull_size) or afull_size is greater than fifo_size, then the port afull will be asserted wheneverthe internal registers are full (address counter = fifo_size).208ModuleWare Reference Manual, Library Version 1.9September 18, 2008