ModuleWare Reference Guide - Hornad

Modulo Counter (modcntr)Sequential PartsModulo Counter (modcntr)This part provides Wait-for as well as Modulo count functionality.The counter has an edge-sensitive trigger on the port clk with the edgecontrolled by the enumerated parameter clk_type. (Rising, Falling). Notethat RisingLast, FallingLast, RisingEdge and FallingEdge are alsosupported for VHDL.The clk port can optionally be enabled by the clk_en port with the polarity(ActiveHigh or ActiveLow) controlled by the enumerated parameterclk_en_type. The default value for this parameter should not be changed ifthe clock enable feature is not going to be used.The counter can operate in one of two modes (Wait-for and Modulo) controlled by theenumerated parameter mode. In Wait-for mode after a reset, the output will be asserted for thefirst time after as many enabled clock cycles as specified by the parameter count. The value ofthe integer parameter count can range from 2 to 65534 (both inclusive). Subsequently, theoutput will be asserted every 2n clock cycles (2n - 1 clock cycles if the style is LFSR), where nis the number of registers required to implement the counter. This results in a more compactimplementation as register reloading is obviated. When operated in Modulo mode, the counterasserts the output every count number of enabled clock cycles after receiving a reset signal.Because registers need to be reloaded, this results in higher gate count.The counter can be reset by means of the rst port. The rst port is controlled by the enumeratedparameter rst_type. When the rst port is asserted (for asynchronous behavior), the internalregisters in the counter are loaded with a value such that the registers are all zero after thespecified number (count) of enabled clock edges have occurred, at which time the output portdout is asserted. The polarity of the assertion of the port dout is controlled by an enumeratedparameter dout_type (ActiveHigh or ActiveLow). For synchronous behavior, the same is trueexcept that the reset action will take place only if the rst port is asserted while an enabled clockedge is also present.The counter has three styles of counting: LFSR (Linear Feedback Shift Register), BinaryIncrement and Binary Decrement. These are controlled by the enumerated parameter style.In Binary Increment and Binary Decrement style, the internal registers are loaded withappropriate values and at each clock edge, the values are incremented or decremented by 1respectively.In LFSR style for counts less than 6, the counter that is actually generated will be a Johnsoncounter (a special case of LFSR) because this is a simpler implementation. The Johnson counterbasically shifts the contents of the registers to the right by one place and fills in the mostsignificant bit with the NOT of the previous least significant bit. For counts greater than 6, thecontents of the registers are shifted to the right by one place and the most significant bit isderived using an appropriate pseudo-random number generation polynomial. LFSR style resultsin significantly reduced gate count compared to the binary increment or decrement styles.To make sure that upon reset the output is asserted after the specified number (count) of clockedges, the reset state must be a unique state. Binary counters with n registers can have aModuleWare Reference Manual, Library Version 1.9 189September 18, 2008