ModuleWare Reference Guide - Hornad

Memory PartsFirst In First Out (fifo)The scalar output port aempty is asserted whenever the address counter is equal to or less thanaempty_size. The default value for aempty_size is zero. For values of aempty_size less than orequal to zero, assertion will take place whenever the internal registers are empty (addresscounter = 0).The part can be triggered on either the rising edge or the falling edge of the scalar input port clk.The polarity of clk is controlled by the enumerated parameter clk_type (Rising, Falling,RisingLast, FallingLast, RisingEdge, FallingEdge).(Note that RisingLast, FallingLast, RisingEdge and FallingEdge are supported for VHDL only.)The clk can optionally be enabled by the scalar input port clk_en. The polarity clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow).The reset operations do not change the values stored inside the internal registers but reset theaddress counter to 0. After a reset operation, further read operations are disabled (until after thenext write) because the FIFO is empty. The mode of reset is controlled by the enumeratedparameter rst_type (SyncActiveHigh, AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).If the input ports clk and rst (for asynchronous behavior) are not enabled the internal registerretains its value.The parameter simultaneous_rw (Allowed, Disallowed) controls whether simultaneous read andwrite operations are enabled.This part is equivalent to a FIFO with n *(fifo_size+1) flip-flops, an address counter and controllogic (where n is the width of the output port ffout).Not using certain operations (not connecting port full or port empty) affects the final gate countand the delay. Leave the clock enable port (clk_en) unconnected if it is not required. The FIFOperformance can be accurately estimated from the parameterized state.The HDL code for the unused optional port is optimized away.Functioncntcreginternal address counterinternal registerIf reset is synchronous, then at every enabled clk trigger (rising edge if clk_type = Rising;falling edge if clk_type = Falling):cnt = 0= cnt + 1= cnt - 1= cntif rst is activated, elseif scalar input port wena is activated and count < fifo_size, elseif scalar input port rena is activated and count > 0otherwiseIf reset is asynchronous:cnt = 0 if input port rst is active (irrespective of the clk trigger), elseModuleWare Reference Manual, Library Version 1.9 209September 18, 2008