ModuleWare Reference Guide - Hornad

Synchronous high rst and positive polarities (for negative polarities invert the values)creg is the internal register.Arithmetic PartsAccumulator (acc)Table 6-5. Accumulator Truth Table — Asynchronous high rst, PositivePolarities (cont.)clk rst load addsub clk_en cregPosedge 0 0 0 1 creg-din-cinTable 6-6. Accumulator Truth Table — Synchronous high rst, PositivePolaritiesclk rst load addsub clk_en creg- - - - 0 cregPosedge 1 - - 1 rst_valPosedge 0 1 - 1 dinposedge 0 0 1 1 creg+din+cinposedge 0 0 0 1 creg-din-cindout= cregParametersTable 6-7. Accumulator ParametersParameter Values Defaultdin, dout Port widths (must be > 0) Automaticrst_valsign_typeload_typecin_typeadd_sub_typerst_typeclk_typeclk_en_typecout_typeReset value (must be >= 0)Unsigned, SignedActiveHigh, ActiveLowActiveHigh, ActiveLowActiveHigh, ActiveLowSyncActiveHigh, AsyncActiveHigh,SyncActiveLow, AsyncActiveLowPolarity (Rising, Falling)ActiveHigh, ActiveLowActiveHigh, ActiveLow0UnsignedActiveHighActiveHighActiveHighAsyncActiveHighRisingActiveHighActiveHighDesign Rule Checks• An error is issued if the width of any port cannot be determined or if any of the ports clk,clk_en, add_sub, load, cin, cout and rst do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of the ports din, load,add_sub, rst, clk or dout are not connected.ModuleWare Reference Manual, Library Version 1.9 105September 18, 2008