ModuleWare Reference Guide - Hornad

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Memory PartsStack (stack)The reset operations do not change the values stored inside the internal registers but reset theaddress counter to 0. After a reset operation, further read operations are disabled (until after thenext write) because the LIFO is empty.The mode of the reset is controlled by the enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow). Do not change the value of theparameter rst_type if the rst port is not used. If input ports clk and rst (for asynchronousbehavior) are not enabled, the internal register retains its value.This part is equivalent to a stack. This part has n *(stack_size+1) flip-flops, the address counterand the control logic (where n is the width of the output port sout). Not using certain operations(not connecting scalar output port full or not connecting scalar output port empty) affects thefinal gate count and the delay. Leave the clock enable port clk_en unconnected if it is notrequired. If clk_en is not connected, the HDL code for the unused port is optimized away.The performance of the stack can be accurately estimated from the parameterized state.Functioncnt is the internal address counter, creg is the internal register.If reset is synchronous:At every enabled clk trigger (rising edge if clk_type = Rising; falling edge if clk_type = Falling):cnt = 0= cnt + 1= cnt - 1= cntif rst is activated, elseif scalar input port push is activated and count < stack_size, elseif scalar input port pop is activated and count > 0, elseotherwiseIf reset is asynchronous:cnt = 0 if input port rst is active (irrespective of the clk trigger), elseat every enabled clk trigger (rising edge if clk_type = Rising; falling edge if clk_type = Falling):cnt = cnt + 1= cnt - 1= cntif scalar input port push is activated and count < stack_size, elseif scalar input port pop is activated and count > 0, elseotherwiseFor a push operation (if cnt < stack_size; and push is enabled)creg(1)sout= sin= creg(0)222ModuleWare Reference Manual, Library Version 1.9September 18, 2008
Memory PartsStack (stack)Truth TableThere are stack_size + 1 internal registers creg (each has a width of input sin). The addresscount is stored in the register cnt. This table is for asynchronous high reset and positivepolarities. For negative polarities, invert the values.Table 9-8. Stack Truth Table — Asynchronous High Reset, Positive Polaritiesclk_en clk rst push pop cnt creg- - 1 - - 0 creg0 - 0 - - cnt creg1 Posedge 0 1 - if (cnt < stack_size)cnt+11 Posedge 0 0 1 if (cnt not equal to 0)cnt -1if (cnt < stack_size)creg[1] = sinif (cnt not equal to 0)creg[cnt] = creg[cnt-1]This table is for synchronous high reset and positive polarities. For negative polarities, invertthe values.Table 9-9. Stack Truth Table — Synchronous High Reset, Positive Polaritiesclk_en clk rst push pop cnt creg0 - - - - cnt creg1 Posedge 1 - - 0 creg-1 Posedge 0 1 - if (cnt < stack_size)cnt+11 Posedge 0 0 1 if (cnt not equal to 0)cnt -1sout = creg[0]empty = (cnt = 0)full = (cnt = stack_size)if (cnt < stack_size)creg[1] = sinif (cnt not equal to 0)creg[cnt] = reg[cnt-1]ModuleWare Reference Manual, Library Version 1.9 223September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
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List of TablesTable 5-18. N-Way Spl
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List of TablesTable 7-20. RS Flip-F
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List of TablesTable 10-41. XNOR Pri
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IntroductionNaming ConventionsNamin
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IntroductionSupported VHDL Packages
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IntroductionReset/Clear BehaviorYou
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IntroductionSet/Preset BehaviorSet/
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IntroductionGate BehaviorFunctioncl
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IntroductionEnable/Load BehaviorFun
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IntroductionVHDL Coding StyleNotes
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IntroductionDesign Rule CheckingFor
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IntroductionSlice SupportOtherwise
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Logic PartsN-Input AND Gate (and)N-
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Logic PartsN-Input XOR Gate (xor)N-
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Logic PartsN-Input NOR Gate (nor)N-
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Logic PartsAssign (assignment)Assig
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Logic PartsBit Setter (bitset)suffi
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Logic PartsBus Driver (busdrive)Bus
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Logic PartsGated OR (or1)Gated OR (
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Logic PartsInverter (inv)Inverter (
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Logic PartsReduction OR (tor)Reduct
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Logic PartsThree-state Buffer (trib
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Logic PartsThree-state bus (tribus)
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Logic PartsVariable Width N-Input A
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Logic PartsVariable Width N-Input X
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ConstantsConstant Value (constval)C
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ConstantsPower (vdd)Power (vdd)This
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Combine
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Combinatorial PartsEncoder (encoder
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Combinatorial PartsN-Input Multiple
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsW-Bit Multiplexe
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Combinatorial PartsW-Bit Multiplexe
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsBus Fill (wor
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Bit Manipulation PartsFixed Bit Sel
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Bit Manipulation PartsFixed Shifter
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Bit Manipulation PartsFixed Shifter
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Arithmetic Parts181 ALU (alu181)181
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Arithmetic Parts181 ALU (alu181)ovf
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Arithmetic PartsAbsolute Value (abs
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Arithmetic PartsAccumulator (acc)ad
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Arithmetic PartsAdder (add)Adder (a
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Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
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Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
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Sequential PartsBank of Flip-Flops
Page 172 and 173: Sequential PartsBank of Flip-Flops
Page 174 and 175: Sequential PartsBank of Latches (la
Page 176 and 177: Sequential PartsClock Divider (clkd
Page 178 and 179: Sequential PartsConfigurable Counte
Page 190 and 191: Sequential PartsModulo Counter (mod
Page 196 and 197: Sequential PartsParallel to Serial
Page 198 and 199: Sequential PartsParallel to Serial
Page 200 and 201: Sequential PartsSerial to Parallel
Page 202 and 203: Sequential PartsThree-state Bank of
Page 204 and 205: Sequential PartsThree-state Bank of
Page 206 and 207: Memory PartsDual Port RAM (ram2p)Du
Page 208 and 209: Memory PartsFirst In First Out (fif
Page 210 and 211: Memory PartsFirst In First Out (fif
Page 212 and 213: Memory PartsSingle Port RAM (ram)Si
Page 214 and 215: Memory PartsRegister File (regfile)
Page 216 and 217: Memory PartsROM (rom)ROM (rom)This
Page 218 and 219: Memory PartsROM (rom)The correspond
Page 220 and 221: Memory PartsROM (rom)Extended segme
Page 224 and 225: Memory PartsStack (stack)Parameters
Page 226 and 227: Memory PartsSynthesizable Dual-Port
Page 228 and 229: Memory PartsSynthesizable Single-Po
Page 230 and 231: Primitive PartsIntroductionIntroduc
Page 232 and 233: Primitive PartsIntroductionTable 10
Page 234 and 235: Primitive PartsBuffer Primitive (pb
Page 236 and 237: Primitive PartsBufif0 Primitive (pb
Page 238 and 239: Primitive PartsBufif1 Primitive (pb
Page 240 and 241: Primitive PartsCMOS Primitive (pcmo
Page 242 and 243: Primitive PartsNAND Primitive (pnan
Page 244 and 245: Primitive PartsNOR Primitive (pnor)
Page 246 and 247: Primitive PartsNOT Primitive (pnot)
Page 248 and 249: Primitive PartsNotif0 Primitive (pn
Page 250 and 251: Primitive PartsNotif1 Primitive (pn
Page 252 and 253: Primitive PartsPMOS Primitive (ppmo
Page 254 and 255: Primitive PartsPullup Primitive (pp
Page 256 and 257: Primitive PartsRCMOS Primitive (prc
Page 258 and 259: Primitive PartsRPMOS Primitive (prp
Page 260 and 261: Primitive PartsXNOR Primitive (pxno
Page 262 and 263: Stimulus PartsSimple Clock (clk)Sim
Page 264 and 265: Stimulus PartsCompound Clock (cmpdc
Page 266 and 267: Stimulus PartsPulse (pulse)Pulse (p
Page 268 and 269: Stimulus PartsConstant Wave (constw
Page 270 and 271: Stimulus PartsRandom Value (random)
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Stimulus PartsRandom Value (random)
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Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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ModuleWare Reference Guide - Hornad

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