ModuleWare Reference Guide - Hornad

Register PartsJK Latch (jklatch)JK Latch (jklatch)This is a highly parameterized JK latch. Upon a trigger of an enabledscalar input port gate, the outputs for the q and qb ports are generatedaccording to the following truth table:Table 7-13. JK Latch Truth Tablej k gate Qn+10 0 High Qn0 1 High 01 0 High 11 1 High QnBThe polarities of the j and k input ports are controlled by the enumerated parameters, j_type andk_type (ActiveHigh, ActiveLow). The j and k input ports can be single bit or buses whichcontrols the corresponding bits of output ports q and qb.The optional output port qb has a bitwise inverted value of the output port q and can be enabledby setting the enumerated parameter qb_type (Enabled, Disabled). Note that using qb does notimply extra inverters, these inverters are usually absorbed by inferred flip-flops because mosthave a qb port.The part can be triggered on the high or the low level of the scalar input port gate. The polarityof the gate port is controlled by the enumerated parameter gate_type (ActiveHigh, ActiveLow).The latch has a scalar input port enable with its mode controlled by the parameter enable_type(AsyncActiveHigh, SyncActiveHigh, AsyncActiveLow, SyncActiveLow, None). Inasynchronous mode, the enable input has a higher priority over the gate input and insynchronous mode, the gate input has a higher priority over the enable input.The register can be preset or cleared to the value of the parameters pre_val and clr_val by usingthe scalar input ports pre and clr. The modes for these ports are controlled by enumeratedparameters pre_type and clr_type (AsyncActiveHigh, SyncActiveHigh, AsyncActiveLow,SyncActiveLow, None). If the mode for these inputs is set to None or if they are unconnected,then the respective pins are not visible in the symbol and the functionality for that pin isdisabled. The modes for these ports can be synchronous or asynchronous.The inferred register depends upon the type of clr and pre behavior. The gate count greatlychanges if the synthesis tool is able to pick up smaller flip-flops.If clr, pre or enable are not connected, the code for unused ports is removed.Parameters pre_val and rst_val can take LNBF format as described in the Constant Value(constval) model, with no limitation on the size of the q and qb ports.The enumerated parameter initialization (Enabled, Disabled) determines whether the localregisters have an initial value.150ModuleWare Reference Manual, Library Version 1.9September 18, 2008