ModuleWare Reference Guide - Hornad

Sequential PartsThree-state Bank of Flip-Flops (triff)Three-state Bank of Flip-Flops (triff)This part provides a bank of flip-flops (register) that have tristate outputs.When the scalar input port clk is triggered, the data from input port din isshifted into the output port q. The output port qb has the bitwise invertedvalue of output port q.The part can be triggered on the rising edge or the falling edge of the scalarinput port clk. The polarity of the scalar input port clk is controlled by theenumerated parameter clk_type (Rising, Falling). Note that RisingLast,FallingLast, RisingEdge and FallingEdge are also supported for VHDL.The clk can optionally be enabled by the scalar input port clk_en. Thepolarity of port clk_en is controlled by the enumerated parameterclk_en_type (ActiveHigh, ActiveLow). Do not change the value of the parameter clk_en_type ifthe clk_en port is not used.The register can be reset to the value of the parameter rst_val by activating the scalar input portrst. The mode of the reset is controlled by the enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow). The output ports can be disabled by thescalar input port oena. The polarity of port oena is controlled by the enumerated parameteroena_type (ActiveHigh, ActiveLow).If the port oena is enabled (oena = 1 for parameter oena_type ActiveHigh and oena = 0 forparameter oena_type = ActiveLow), the values stored in the flip-flops are placed in the outputports.If the port oena is disabled, the value Z is placed in every bit of the output ports. (Note that inthis case, both the output ports become Z.) If input ports clk and rst (for asynchronousbehavior) are not enabled, the outputs of the flip-flops retain their values.This part is equivalent to n flip-flops; where n is the width of the ports din, q and qb. Theinferred register depends upon the type of reset behavior. The gate count greatly changes if thesynthesis tool is able to pick up smaller flip-flops. Note that using qb does not imply extrainverters, these inverters are usually absorbed by inferred flip-flop because most have a qb port.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the scalarinput port clk_en must be unconnected and the parameter clk_en_type must be set toActiveHigh. Port clk_en can also be driven by an active driver, in which case the clk_en_typemust be correctly adjusted.The HDL code for unused optional ports is optimized away.Parameter rst_val can take LNBF format as described in the Constant Value (constval) modelwith no limitation on the size of the q and qb ports.FunctionAn enabled clk trigger is a trigger that occurs when input port clk_en is active.202ModuleWare Reference Manual, Library Version 1.9September 18, 2008