ModuleWare Reference Guide - Hornad

IntroductionReset/Clear BehaviorYou are advised not to edit the value of the parameter rst_type if port rst is not connectedbecause this can modify the default operation. The polarity of the rst port is implemented in thegenerated HDL code.Most of the sequential parts have a parameter to specify the value to which the part is reset. Thisparameter is always named rst_val.Note that this operation deviates from the traditional method of having a clear and set port,where clear puts in the value of 0 and set puts the value of 1. The rst port in the ModuleWareparts has been parameterized to handle both these functions but the effect of this is that the useris forced to choose one value. This was done to avoid having too many parameters because themajority of designs require only one rst port.The reset function sets the value of the register to a particular value (rst_val) which means that,in the post-synthesis netlist, some of these inferred registers could have a clear port and others aset port. All zeros and all ones are a subset of this value. If the value of the parameter rst_valexceeds the maximum allowed by the register, the lower bits are chosen and a warning is issuedfor such cases. A synchronous reset could also be implemented with logical gates connected tothe input of the sequential part.Functionrst_type = SyncActiveHighrst_type = AsyncActiveHighrst_type = SyncActiveLowrst_type = AsyncActiveLowsynchronous, positive polarityasynchronous, positive polaritysynchronous, negative polarity ( )asynchronous, negative polarity ( )Notes• The default value for the parameter rst_type is AsyncActiveHigh.• Leave the port rst unconnected if not used and do not change the value of parameterrst_type.• The rst port is always on the top of the symbol.Reset/Clear BehaviorThis functionality is available only on the Register parts using the rst or clr input ports. A partcan be reset or cleared asynchronously or synchronously. A part could be reset or cleared with avalue of 0 or 1 on the rst or clr port. This behavior of the rst and clr ports is controlled by theparameters rst_type and clr_type.• For all the parts with a rst/clr port, the parameters rst_type and clr_type are enumeratedwith the values AsyncActiveHigh, SyncActiveHigh, AsyncActiveLow andSyncActiveLow.20ModuleWare Reference Manual, Library Version 1.9September 18, 2008