ModuleWare Reference Guide - Hornad

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Primitive PartsCMOS Primitive (pcmos)CMOS Primitive (pcmos)This is a highly parameterized cmos primitive which has a scalar input, ascalar output and two control inputs.The rise, fall and turnoff delays can be specified by separate enumeratedparameters rise_delay, fall_delay and turnoff_delay respectively.If there is no delay specification, there is no propagation delay throughthe gate.If turnoff_delay is not specified, the smallest of the rise and fall delaysapplies on output transitions to X and Z. If turnoff_delay is specified, it determines the delay oftransitions to Z, and the smallest of the three delays determines the delay of transitions to X.Some combinations of data input values and control input values cause these gates to output oneof the two values without a preference for either value. The logic table for this gate includes twovalues representing such unknown results. The value L is a result representative of a value of 0or Z. The value H is a result representative of a value of 1 or Z.Functiondout = din generated according to the following truth tablesTruth TableTable 10-11. CMOS Primitive Truth Tablepcmos Control (pena)0 1 X ZD 0 0 Z L LA 1 1 Z H HT X X Z X XA Z Z Z Z ZTable 10-12. CMOS Primitive Truth Tablepcmos Control (nena)0 1 X ZD 0 Z 0 L LA 1 Z 1 H HT X Z X X XA Z Z Z Z Z240ModuleWare Reference Manual, Library Version 1.9September 18, 2008
Primitive PartsCMOS Primitive (pcmos)ParametersTable 10-13. CMOS Primitive ParametersParameter Values Defaultfall_delayrise_delayturnoff_delayInteger value of the fall time for the gateInteger value of the rise time for the gateInteger value of the turnoff time for the gateDesign Rule Checks• An error is issued if the width of any port cannot be determined, if ports din, dout, pena andnena do not have a fixed width of 1 or if both strength types are set to HighZ.• A warning is issued and HDL generation fails for this part if any of ports are not connected.000ModuleWare Reference Manual, Library Version 1.9 241September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
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List of TablesTable 5-18. N-Way Spl
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List of TablesTable 7-20. RS Flip-F
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List of TablesTable 10-41. XNOR Pri
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IntroductionNaming ConventionsNamin
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IntroductionSupported VHDL Packages
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IntroductionReset/Clear BehaviorYou
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IntroductionSet/Preset BehaviorSet/
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IntroductionGate BehaviorFunctioncl
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IntroductionEnable/Load BehaviorFun
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IntroductionVHDL Coding StyleNotes
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IntroductionDesign Rule CheckingFor
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IntroductionSlice SupportOtherwise
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Logic PartsN-Input AND Gate (and)N-
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Logic PartsN-Input XOR Gate (xor)N-
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Logic PartsN-Input NOR Gate (nor)N-
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Logic PartsAssign (assignment)Assig
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Logic PartsBit Setter (bitset)suffi
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Logic PartsBus Driver (busdrive)Bus
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Logic PartsGated OR (or1)Gated OR (
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Logic PartsInverter (inv)Inverter (
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Logic PartsReduction OR (tor)Reduct
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Logic PartsThree-state Buffer (trib
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Logic PartsThree-state bus (tribus)
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Logic PartsVariable Width N-Input A
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Logic PartsVariable Width N-Input X
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ConstantsConstant Value (constval)C
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ConstantsPower (vdd)Power (vdd)This
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Combine
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Combinatorial PartsEncoder (encoder
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Combinatorial PartsN-Input Multiple
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsW-Bit Multiplexe
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Combinatorial PartsW-Bit Multiplexe
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsBus Fill (wor
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Bit Manipulation PartsFixed Bit Sel
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Bit Manipulation PartsFixed Shifter
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Bit Manipulation PartsFixed Shifter
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Arithmetic Parts181 ALU (alu181)181
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Arithmetic Parts181 ALU (alu181)ovf
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Arithmetic PartsAbsolute Value (abs
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Arithmetic PartsAccumulator (acc)ad
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Arithmetic PartsAdder (add)Adder (a
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Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
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Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Latches (la
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Sequential PartsClock Divider (clkd
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Sequential PartsConfigurable Counte
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Page 190 and 191: Sequential PartsModulo Counter (mod
Page 196 and 197: Sequential PartsParallel to Serial
Page 198 and 199: Sequential PartsParallel to Serial
Page 200 and 201: Sequential PartsSerial to Parallel
Page 202 and 203: Sequential PartsThree-state Bank of
Page 204 and 205: Sequential PartsThree-state Bank of
Page 206 and 207: Memory PartsDual Port RAM (ram2p)Du
Page 208 and 209: Memory PartsFirst In First Out (fif
Page 210 and 211: Memory PartsFirst In First Out (fif
Page 212 and 213: Memory PartsSingle Port RAM (ram)Si
Page 214 and 215: Memory PartsRegister File (regfile)
Page 216 and 217: Memory PartsROM (rom)ROM (rom)This
Page 218 and 219: Memory PartsROM (rom)The correspond
Page 220 and 221: Memory PartsROM (rom)Extended segme
Page 222 and 223: Memory PartsStack (stack)The reset
Page 224 and 225: Memory PartsStack (stack)Parameters
Page 226 and 227: Memory PartsSynthesizable Dual-Port
Page 228 and 229: Memory PartsSynthesizable Single-Po
Page 230 and 231: Primitive PartsIntroductionIntroduc
Page 232 and 233: Primitive PartsIntroductionTable 10
Page 234 and 235: Primitive PartsBuffer Primitive (pb
Page 236 and 237: Primitive PartsBufif0 Primitive (pb
Page 238 and 239: Primitive PartsBufif1 Primitive (pb
Page 242 and 243: Primitive PartsNAND Primitive (pnan
Page 244 and 245: Primitive PartsNOR Primitive (pnor)
Page 246 and 247: Primitive PartsNOT Primitive (pnot)
Page 248 and 249: Primitive PartsNotif0 Primitive (pn
Page 250 and 251: Primitive PartsNotif1 Primitive (pn
Page 252 and 253: Primitive PartsPMOS Primitive (ppmo
Page 254 and 255: Primitive PartsPullup Primitive (pp
Page 256 and 257: Primitive PartsRCMOS Primitive (prc
Page 258 and 259: Primitive PartsRPMOS Primitive (prp
Page 260 and 261: Primitive PartsXNOR Primitive (pxno
Page 262 and 263: Stimulus PartsSimple Clock (clk)Sim
Page 264 and 265: Stimulus PartsCompound Clock (cmpdc
Page 266 and 267: Stimulus PartsPulse (pulse)Pulse (p
Page 268 and 269: Stimulus PartsConstant Wave (constw
Page 270 and 271: Stimulus PartsRandom Value (random)
Page 272 and 273: Stimulus PartsRandom Value (random)
Page 274 and 275: Stimulus PartsCounter Value (counte
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Page 278 and 279: Name ListName Description Pagedlatc
Page 280 and 281: Name ListName Description Pagesplit
Page 282 and 283: Function ListFunction Description P
Page 284 and 285: Function ListFunction Description P
Page 286 and 287: Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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