ModuleWare Reference Guide - Hornad

Clock Divider (clkdiv)Sequential PartsClock Divider (clkdiv)This part allows you to divide a clock into smaller frequency clocks.The frequency of the output clock (scalar output port clk_out) is thefrequency of the scalar input clock port (clk) divided by the value ofthe parameter divide_by. For example, a value of 4 for parameterdivide_by provides an output clock that is 4 times slower.The value of the parameter duty_cycle controls the position of therising edge. In every cycle (time period of clk * divide_by), theoutput begins with a value 0 and has one rising edge during thecycle. The value of the parameter duty_cycle gives the number of time periods of scalar inputport clk for which the output is 1.The part can be reset by the scalar input port rst. The reset operation resets the internal counterto a 0. The reset operation always puts the clock divider back to the start of the output clockperiod.The part can be triggered on the rising edge or the falling edge of the scalar input port clk. Thepolarity of port clk is controlled by the enumerated parameter clk_type (Rising, Falling). Notethat RisingLast, FallingLast, RisingEdge and FallingEdge are also supported for VHDL.The clk can optionally be enabled by the scalar input port clk_en. The polarity of clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of the parameter clk_en_type if the clk_en port is not used.The register can be reset to the value of the parameter rst_val by activating the scalar input portrst. The reset mode is controlled by the parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow). If the reset functionality is not used, donot change the value of the parameter rst_type.This part is equivalent to a clock divider. The performance cannot be estimated because itdepends on the synthesis tools. A clock divider has many possible counter implementationssuch as a binary counter, LFSR counter or one-hot counter. You are advised to carefully controlthe implementation via synthesis scripts based on the requirements.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the scalarinput port clk_en must be unconnected and the parameter clk_en_type must be set toActiveHigh. Port clk_en can also be driven by an active driver, in which case the clk_en_typemust be correctly adjusted. The HDL code for clk_en is optimized away if it is not used.A reset operation must be performed on this part for proper function. If the part is not reset, thesimulation part will work but the post synthesis part does not. This is because reset is the onlyway to load a value in the internal register.ModuleWare Reference Manual, Library Version 1.9 175September 18, 2008