ModuleWare Reference Guide - Hornad

Memory PartsFirst In First Out (fifo)ParametersTable 9-4. First In First Out ParametersParameter Values Defaultffin, ffout Port widths (must be > 0) Automaticaempty_typeafull_typeclk_typeclk_en_typeempty_typefull_typerena_typerst_typewena_typeaempty_sizeafull_sizefifo_sizesimultaneous_rwActiveHigh,ActiveLowActiveHigh,ActiveLowRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLowActiveHigh,ActiveLowActiveHigh,ActiveLowActiveHigh,ActiveLowSyncActiveHigh,AsyncActiveHigh,SyncActiveLow,AsyncActiveLowActiveHigh,ActiveLowAlmost-empty condition evaluationAlmost-full condition evaluationFIFO size (maximum number of data elements)Allowed,Disallowed (simultaneous read and write)ActiveHighActiveHighRisingActiveHighActiveHighActiveHighActiveHighAsyncActiveHighActiveHigh000DisallowedDesign Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, clk_en, rst,wena, rena, full and empty do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports ffin, ffout, wena,rena, clk or rst are not connected.ModuleWare Reference Manual, Library Version 1.9 211September 18, 2008