ModuleWare Reference Guide - Hornad

Register PartsT Latch (tlatch)Synchronous rst and set and asynchronous enable:Table 7-37. T Latch Truth Table — Synchronous rst and set, Asynchronousenableenable gate rst set q qb- - 1 - / NC q qb- - 0 / NC 1 q qb1 / NC 1 1 0 / NC rst_val NOT(rst_val)1 / NC 1 0 / NC 1 set_val NOT(set_val)NC 1 0 / NC 0 / NC T TT NOT(T TT)0 1 0 / NC 0 / NC q qb1 1 0 / NC 0 / NC T TT NOT(T TT)ParametersTable 7-38. T Latch ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticenable_typegate_typeqb_typerst_typeset_typeinitializationrst_valset_valAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLowEnabled,DisabledAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister reset value (must be >= 0)Register set value (must be >= 0)SyncActiveHighActiveHighEnabledAsyncActiveHighAsyncActiveHighDisabled01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports gate, enable, rstand set do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if port gate is not connected or ifat least one of ports q and qb are not connected.ModuleWare Reference Manual, Library Version 1.9 167September 18, 2008