ModuleWare Reference Guide - Hornad

Register PartsRS Latch (rslatch)Synchronous rst and set and asynchronous enable:Table 7-27. RS Latch Truth Table — Synchronous rst and set, Asynchronousenableenable gate rst set q qb- - 1 - / NC q qb- - 0 / NC 1 q qb1 / NC 1 1 0 / NC rst_val NOT(rst_val)1 / NC 1 0 / NC 1 set_val NOT(set_val)NC 1 0 / NC 0 / NC RS TT NOT(RS TT)0 1 0 / NC 0 / NC q qb1 1 0 / NC 0 / NC RS TT NOT(RS TT)ParametersTable 7-28. RS Latch ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticenable_typegate_typeqb_typer_typerst_types_typeset_typeinitializationrs_priorityrst_valset_valAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLowEnabled,DisabledActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneActiveHigh,ActiveLowAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledR-S,S-RRegister reset value (must be >= 0)Register set value (must be >= 0)SyncActiveHighActiveHighEnabledActiveHighAsyncActiveHighActiveHighAsyncActiveHighDisabledR-S01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports gate, enable, rst,set, r and s do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if any of ports r, s or gate are notconnected or if at least one of ports q and qb are not connected.160ModuleWare Reference Manual, Library Version 1.9September 18, 2008