ModuleWare Reference Guide - Hornad

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Memory PartsROM (rom)Extended segment address records contain bits 4 to 9 of the data address and act as an offset forall subsequent data records. The value remains in effect until changed by another extendedsegment address record.The extended segment address record always has 2 data bytes and is of the form:NoteExtended segment address records are not supported by the ROM generator.An Intel HEX file must end with an end-of-file (EOF) record. This record must have the value01 in the record type field. An EOF record always appears as follows:Example HEX file:220ModuleWare Reference Manual, Library Version 1.9September 18, 2008
Stack (stack)Memory PartsStack (stack)This part implements a stack. Data can be loaded (pushed) into theinternal registers and read (popped) at a later time. All operations inthis part (except for reset) are synchronous with respect to the clock.The depth is controlled by the parameter stack_size. The stacksupports two input/output operations.A push operation takes the value of the input port sin and places it inthe internal registers.A pop operation takes the newest value in the internal registers andplaces it in the output port sout. This value is retained on sout, untilthe next pop operation.The pop operation is controlled by the scalar input port pop. Thepush operation is controlled by the scalar input port push and hasprecedence over the pop operation.The polarity of the scalar input port pop is controlled by the enumerated parameter pop_type(ActiveHigh, ActiveLow). The polarity of the scalar output port push is controlled by theenumerated parameter push_type (ActiveHigh, ActiveLow).The part consists of the required number of the internal registers, an address counter and thecontrol logic. The address counter keeps count of the current address. This value is used todisable the pop and push operations. This counter decides whether the stack is empty (counter =0) or full (counter = stack_size). The reset operation is required before a correct operation of thestack (for post synthesis simulation match). Pop operations cannot be done before a pushoperation.Push operations are disabled if the internal registers are full (address counter = stack_size). Popoperations are disabled in the internal registers are empty (address counter = 0). If the internalregisters are full and both push and pop operations are triggered, the pop operation takes place.Only when the internal registers are full does the pop operation takes precedence over the push(because write is disabled). Scalar output port full is activated if the internal registers are full.Scalar output port empty is activated if the internal registers are empty. The polarity of thescalar output port full is controlled by the enumerated parameter full_type (ActiveHigh,ActiveLow). The polarity of the scalar output port empty is controlled by the enumeratedparameter empty_type (ActiveHigh, ActiveLow).The part can be triggered on either the rising or falling edge of the scalar input port clk. Thepolarity of clk is controlled by the enumerated parameter clk_type (Rising, Falling, RisingLast,FallingLast, RisingEdge, FallingEdge).(Note that RisingLast, FallingLast, RisingEdge and FallingEdge are supported for VHDL only.)The clk can optionally be enabled by the scalar input port clk_en. The polarity of clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of the parameter clk_en_type, if the clk_en port is not used.ModuleWare Reference Manual, Library Version 1.9 221September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
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List of TablesTable 5-18. N-Way Spl
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List of TablesTable 7-20. RS Flip-F
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List of TablesTable 10-41. XNOR Pri
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IntroductionNaming ConventionsNamin
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IntroductionSupported VHDL Packages
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IntroductionReset/Clear BehaviorYou
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IntroductionSet/Preset BehaviorSet/
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IntroductionGate BehaviorFunctioncl
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IntroductionEnable/Load BehaviorFun
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IntroductionVHDL Coding StyleNotes
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IntroductionDesign Rule CheckingFor
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IntroductionSlice SupportOtherwise
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Logic PartsN-Input AND Gate (and)N-
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Logic PartsN-Input XOR Gate (xor)N-
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Logic PartsN-Input NOR Gate (nor)N-
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Logic PartsAssign (assignment)Assig
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Logic PartsBit Setter (bitset)suffi
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Logic PartsBus Driver (busdrive)Bus
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Logic PartsGated OR (or1)Gated OR (
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Logic PartsInverter (inv)Inverter (
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Logic PartsReduction OR (tor)Reduct
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Logic PartsThree-state Buffer (trib
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Logic PartsThree-state bus (tribus)
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Logic PartsVariable Width N-Input A
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Logic PartsVariable Width N-Input X
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ConstantsConstant Value (constval)C
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ConstantsPower (vdd)Power (vdd)This
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Separat
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Combinatorial PartsDecoder, Combine
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Combinatorial PartsEncoder (encoder
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Combinatorial PartsN-Input Multiple
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsN-Input One-hot
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Combinatorial PartsW-Bit Multiplexe
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Combinatorial PartsW-Bit Multiplexe
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Bus Merge (
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsN-Way Splitte
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Bit Manipulation PartsBus Fill (wor
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Bit Manipulation PartsFixed Bit Sel
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Bit Manipulation PartsFixed Shifter
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Bit Manipulation PartsFixed Shifter
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Arithmetic Parts181 ALU (alu181)181
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Arithmetic Parts181 ALU (alu181)ovf
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Arithmetic PartsAbsolute Value (abs
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Arithmetic PartsAccumulator (acc)ad
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Arithmetic PartsAdder (add)Adder (a
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Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
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Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
Page 170 and 171: Sequential PartsBank of Flip-Flops
Page 172 and 173: Sequential PartsBank of Flip-Flops
Page 174 and 175: Sequential PartsBank of Latches (la
Page 176 and 177: Sequential PartsClock Divider (clkd
Page 178 and 179: Sequential PartsConfigurable Counte
Page 190 and 191: Sequential PartsModulo Counter (mod
Page 196 and 197: Sequential PartsParallel to Serial
Page 198 and 199: Sequential PartsParallel to Serial
Page 200 and 201: Sequential PartsSerial to Parallel
Page 202 and 203: Sequential PartsThree-state Bank of
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Page 206 and 207: Memory PartsDual Port RAM (ram2p)Du
Page 208 and 209: Memory PartsFirst In First Out (fif
Page 210 and 211: Memory PartsFirst In First Out (fif
Page 212 and 213: Memory PartsSingle Port RAM (ram)Si
Page 214 and 215: Memory PartsRegister File (regfile)
Page 216 and 217: Memory PartsROM (rom)ROM (rom)This
Page 218 and 219: Memory PartsROM (rom)The correspond
Page 222 and 223: Memory PartsStack (stack)The reset
Page 224 and 225: Memory PartsStack (stack)Parameters
Page 226 and 227: Memory PartsSynthesizable Dual-Port
Page 228 and 229: Memory PartsSynthesizable Single-Po
Page 230 and 231: Primitive PartsIntroductionIntroduc
Page 232 and 233: Primitive PartsIntroductionTable 10
Page 234 and 235: Primitive PartsBuffer Primitive (pb
Page 236 and 237: Primitive PartsBufif0 Primitive (pb
Page 238 and 239: Primitive PartsBufif1 Primitive (pb
Page 240 and 241: Primitive PartsCMOS Primitive (pcmo
Page 242 and 243: Primitive PartsNAND Primitive (pnan
Page 244 and 245: Primitive PartsNOR Primitive (pnor)
Page 246 and 247: Primitive PartsNOT Primitive (pnot)
Page 248 and 249: Primitive PartsNotif0 Primitive (pn
Page 250 and 251: Primitive PartsNotif1 Primitive (pn
Page 252 and 253: Primitive PartsPMOS Primitive (ppmo
Page 254 and 255: Primitive PartsPullup Primitive (pp
Page 256 and 257: Primitive PartsRCMOS Primitive (prc
Page 258 and 259: Primitive PartsRPMOS Primitive (prp
Page 260 and 261: Primitive PartsXNOR Primitive (pxno
Page 262 and 263: Stimulus PartsSimple Clock (clk)Sim
Page 264 and 265: Stimulus PartsCompound Clock (cmpdc
Page 266 and 267: Stimulus PartsPulse (pulse)Pulse (p
Page 268 and 269: Stimulus PartsConstant Wave (constw
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Stimulus PartsRandom Value (random)
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Stimulus PartsRandom Value (random)
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Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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