ModuleWare Reference Guide - Hornad

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ConstantsConstant Value (constval)Constant Value (constval)This part is a constant value driver. The parameter value must be entered in LNBFformat which supports decimal, binary, hexadecimal, and octal radix.The valid LNBF format is: the radix notation letter (h for hexadecimal, b forbinary, o for octal, d for decimal) followed by # followed by a number in thespecified radix. If you omit the radix notation letter, the radix will de defaulted to decimal. Forexample: h#fc (hexadecimal); o#12 (octal); b#10011001 (binary); d#10 or 10 (decimal).If the convert_value parameter is enabled, the dout port is assigned the binary value for VHDLor retains the entered value for Verilog.If the convert_value parameter is disabled, the entered value is assigned to the dout port forboth VHDL and Verilog without any modifications.This part is equivalent to n 1-bit Vdd or Ground, where n is the port width.Functiondout = valueParametersTable 3-1. Constant Value ParametersParameter Values Defaultdout Port width (must be > 0) Automaticconvert_valuevalueEnabled, DisabledThe parameter value (must be > 0)Enabled0Design Rule Checks• An error is issued if any of the width of the dout port cannot be determined, the valueparameter has no value or if the width of the parameter value (after representing it in binary)is greater than the dout port width.• A warning is issued and HDL generation fails for this part if the dout port is not connected.60ModuleWare Reference Manual, Library Version 1.9September 18, 2008
ConstantsGround (gnd)Ground (gnd)This part is a 0 value driver. A 0 is placed in output port dout.This part is equivalent to n 1-bit Ground, where n is the port width.Functiondout = 0 (for every bit)ParametersTable 3-2. Ground ParametersParameter Values Defaultdout Port width (must be > 0) AutomaticDesign Rule Checks• An error is issued if any of the width of the dout port cannot be determined.• A warning is issued and HDL generation fails for this part if the dout port is not connected.ModuleWare Reference Manual, Library Version 1.9 61September 18, 2008
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ModuleWare Reference Manualfor the
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Table of ContentsGated OR (or1) . .
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Table of ContentsBufif0 Primitive (
Page 9 and 10: List of TablesTable 5-18. N-Way Spl
Page 11 and 12: List of TablesTable 7-20. RS Flip-F
Page 14 and 15: List of TablesTable 10-41. XNOR Pri
Page 16 and 17: IntroductionNaming ConventionsNamin
Page 18 and 19: IntroductionSupported VHDL Packages
Page 20 and 21: IntroductionReset/Clear BehaviorYou
Page 22 and 23: IntroductionSet/Preset BehaviorSet/
Page 24 and 25: IntroductionGate BehaviorFunctioncl
Page 26 and 27: IntroductionEnable/Load BehaviorFun
Page 28 and 29: IntroductionVHDL Coding StyleNotes
Page 30 and 31: IntroductionDesign Rule CheckingFor
Page 32 and 33: IntroductionSlice SupportOtherwise
Page 34 and 35: Logic PartsN-Input AND Gate (and)N-
Page 36 and 37: Logic PartsN-Input XOR Gate (xor)N-
Page 38 and 39: Logic PartsN-Input NOR Gate (nor)N-
Page 40 and 41: Logic PartsAssign (assignment)Assig
Page 42 and 43: Logic PartsBit Setter (bitset)suffi
Page 44 and 45: Logic PartsBus Driver (busdrive)Bus
Page 46 and 47: Logic PartsGated OR (or1)Gated OR (
Page 48 and 49: Logic PartsInverter (inv)Inverter (
Page 50 and 51: Logic PartsReduction OR (tor)Reduct
Page 52 and 53: Logic PartsThree-state Buffer (trib
Page 54 and 55: Logic PartsThree-state bus (tribus)
Page 56 and 57: Logic PartsVariable Width N-Input A
Page 58 and 59: Logic PartsVariable Width N-Input X
Page 62 and 63: ConstantsPower (vdd)Power (vdd)This
Page 64 and 65: Combinatorial PartsDecoder, Separat
Page 66 and 67: Combinatorial PartsDecoder, Separat
Page 68 and 69: Combinatorial PartsDecoder, Combine
Page 70 and 71: Combinatorial PartsEncoder (encoder
Page 72 and 73: Combinatorial PartsN-Input Multiple
Page 74 and 75: Combinatorial PartsN-Input One-hot
Page 76 and 77: Combinatorial PartsN-Input One-hot
Page 78 and 79: Combinatorial PartsW-Bit Multiplexe
Page 80 and 81: Combinatorial PartsW-Bit Multiplexe
Page 82 and 83: Bit Manipulation PartsN-Bus Merge (
Page 84 and 85: Bit Manipulation PartsN-Bus Merge (
Page 86 and 87: Bit Manipulation PartsN-Way Splitte
Page 88 and 89: Bit Manipulation PartsN-Way Splitte
Page 90 and 91: Bit Manipulation PartsBus Fill (wor
Page 92 and 93: Bit Manipulation PartsFixed Bit Sel
Page 94 and 95: Bit Manipulation PartsFixed Shifter
Page 96 and 97: Bit Manipulation PartsFixed Shifter
Page 98 and 99: Arithmetic Parts181 ALU (alu181)181
Page 100 and 101: Arithmetic Parts181 ALU (alu181)ovf
Page 102 and 103: Arithmetic PartsAbsolute Value (abs
Page 104 and 105: Arithmetic PartsAccumulator (acc)ad
Page 106 and 107: Arithmetic PartsAdder (add)Adder (a
Page 108 and 109: Arithmetic PartsAdder (add)Table 6-
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsAdder Subtractor (a
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Arithmetic PartsComparator (cmp)Com
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Arithmetic PartsDecrementer (dec)De
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Arithmetic PartsIncrementer (inc)In
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsIncrementer Decreme
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Arithmetic PartsLeft Shifter (lshif
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Arithmetic PartsMultiplier (mult)A
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Arithmetic PartsRight Shifter (rshi
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Arithmetic PartsSubtractor (sub)Sub
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Arithmetic PartsSubtractor (sub)Tab
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Arithmetic PartsUni-function Compar
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Arithmetic PartsVariable Shifter (v
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Arithmetic PartsVariable Shifter (v
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Register PartsD Flip-Flop (adff)D F
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Register PartsD Flip-Flop (adff)Par
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Register PartsD Latch (dlatch)If lo
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Register PartsD Latch (dlatch)Table
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Register PartsJK Flip-Flop (jkff)Fu
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Register PartsJK Latch (jklatch)JK
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Register PartsJK Latch (jklatch)Asy
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Register PartsRS Flip-Flop (rsff)RS
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Register PartsRS Flip-Flop (rsff)Ta
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Register PartsRS Latch (rslatch)Fun
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Register PartsRS Latch (rslatch)Syn
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Register PartsT Flip-Flop (tff)Func
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Register PartsT Latch (tlatch)T Lat
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Register PartsT Latch (tlatch)Async
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Register PartsT Latch (tlatch)168Mo
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Flip-Flops
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Sequential PartsBank of Latches (la
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Sequential PartsClock Divider (clkd
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Sequential PartsConfigurable Counte
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Sequential PartsModulo Counter (mod
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Sequential PartsParallel to Serial
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Sequential PartsParallel to Serial
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Sequential PartsSerial to Parallel
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Sequential PartsThree-state Bank of
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Sequential PartsThree-state Bank of
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Memory PartsDual Port RAM (ram2p)Du
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Memory PartsFirst In First Out (fif
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Memory PartsFirst In First Out (fif
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Memory PartsSingle Port RAM (ram)Si
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Memory PartsRegister File (regfile)
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Memory PartsROM (rom)ROM (rom)This
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Memory PartsROM (rom)The correspond
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Memory PartsROM (rom)Extended segme
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Memory PartsStack (stack)The reset
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Memory PartsStack (stack)Parameters
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Memory PartsSynthesizable Dual-Port
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Memory PartsSynthesizable Single-Po
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Primitive PartsIntroductionIntroduc
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Primitive PartsIntroductionTable 10
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Primitive PartsBuffer Primitive (pb
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Primitive PartsBufif0 Primitive (pb
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Primitive PartsBufif1 Primitive (pb
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Primitive PartsCMOS Primitive (pcmo
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Primitive PartsNAND Primitive (pnan
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Primitive PartsNOR Primitive (pnor)
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Primitive PartsNOT Primitive (pnot)
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Primitive PartsNotif0 Primitive (pn
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Primitive PartsNotif1 Primitive (pn
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Primitive PartsPMOS Primitive (ppmo
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Primitive PartsPullup Primitive (pp
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Primitive PartsRCMOS Primitive (prc
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Primitive PartsRPMOS Primitive (prp
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Primitive PartsXNOR Primitive (pxno
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Stimulus PartsSimple Clock (clk)Sim
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Stimulus PartsCompound Clock (cmpdc
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Stimulus PartsPulse (pulse)Pulse (p
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Stimulus PartsConstant Wave (constw
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Stimulus PartsRandom Value (random)
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Stimulus PartsRandom Value (random)
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Stimulus PartsCounter Value (counte
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Stimulus PartsCounter Value (counte
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Name ListName Description Pagedlatc
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Name ListName Description Pagesplit
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Function ListFunction Description P
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Function ListFunction Description P
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Function List286ModuleWare Referenc
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A BC D E F G H I J K L M N O P Q R
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A BC D E F G H I J K L M N O P Q R
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4. RESTRICTIONS ON USE. You may cop
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15. CONTROLLING LAW, JURISDICTION A
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ModuleWare Reference Guide - Hornad

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