ModuleWare Reference Guide - Hornad

Register PartsD Flip-Flop (adff)ParametersTable 7-3. D Flip-Flop ParametersParameter Values Defaultd, q, qb Port widths (must be > 0) Automaticclk_typeload_typeqb_typerst_typeset_typeinitializationrst_valset_valRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLow,NoneEnabled,DisabledAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister reset value (must be >= 0)Register set value (must be >= 0)RisingActiveHighEnabledAsyncActiveHighAsyncActiveHighDisabled01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, load, rst, andset do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if either ports d and clk are notconnected or if at least one of ports q and qb are not connected.142ModuleWare Reference Manual, Library Version 1.9September 18, 2008