ModuleWare Reference Guide - Hornad

Parallel to Serial Shifter (shiftps)Sequential PartsParallel to Serial Shifter (shiftps)This part allows you to load data into the shift register and shift outthis data one bit at a time. The resultant bit is placed in the scalaroutput port dout. The number of internal flip-flops used is equal tothe width of the input data port din. A new value can be loaded intothe internal register by loading the value of the input data port din orby the reset operation. The reset operation has the highest priority.The load operation is controlled by the scalar input port load. Thevalue of input data port din is loaded when the scalar input port loadis activated. The load operation is synchronous with respect to thescalar input port clk.A shift operation takes place on the internal register in the absence ofa load operation or a reset operation. During the shift operation, the internal register is shifted by1. The shift operation can be performed in one of three modes set by the enumerated parametermode (Logical, Arithmetic, Circular).The direction of the shift is decided by the scalar input port rl. If port rl is activated, the shiftright operation is executed. If port rl is deactivated, a shift left operation is executed. Thepolarity of port rl is controlled by the enumerated parameter rl_type (ActiveHigh, ActiveLow).Port rl is considered activated if its value is 1 and the polarity is ActiveHigh, or its value is 0and the polarity is ActiveLow. For Logical mode, 0 is shifted in (for both left and right shiftoperations). For Arithmetic mode, 0 is shifted into the LSB for left shift but for the right shiftthe MSB is retained. For Circular mode, the right shift involves shifting the LSB to the MSBwhile the left shift involves shifting the MSB to the LSB.The part can be triggered on the rising edge or the falling edge of port clk. The polarity of portclk is controlled by the enumerated parameter clk_type (Rising, Falling). Note that RisingLast,FallingLast, RisingEdge and FallingEdge are also supported for VHDL.The clk can optionally be enabled by the scalar input port clk_en. The polarity port clk_en iscontrolled by the enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not changethe value of the parameter clk_en_type if the clk_en port is not used.The register can be reset to the value of parameter rst_val by activating the scalar input port rst.The reset mode is controlled by the enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow).If the input ports clk and rst (for asynchronous behavior) are not enabled the internal registerretains its value.The scalar output port gets the value of the MSB or the LSB of the internal register. If the scalarinput port rl is activated (RIGHT shift), the scalar output port dout get the value of the LSB ofthe internal register. If the scalar input port rl is not activated (LEFT shift), the scalar outputport dout get the value of the MSB of the internal register. Note that this is true even during areset operation or a load operation.ModuleWare Reference Manual, Library Version 1.9 195September 18, 2008