ModuleWare Reference Guide - Hornad

Memory PartsFirst In First Out (fifo)at every enabled clk trigger (rising edge if clk_type = Rising; falling edge if clk_type = Falling):cnt = cnt + 1= cnt - 1= cntif scalar input port wena is activated and count < fifo_size, elseif scalar input port rena is activated and count > 0, elseotherwiseFor a write operation (if cnt < fifo_size; and wena is enabled):creg(cnt)ffout= ffin= creg(0)Truth TableThe following tables are for positive polarities. For negative polarities, invert the values. Thereare fifo_size + 1 internal registers (creg) (each has a width of input ffin). The address count isstored in the register cnt.This table is for asynchronous high reset.Table 9-2. First In First Out Truth Table — Asynchronous High Resetwena rena clk_en clk rst cnt creg- - - - 1 0 creg- - 0 - 0 cnt creg1 - 1 posedge 0 if (cnt < fifo_size)cnt+10 1 1 posedge 0 if (cnt not equal to 0)cnt -1This table is for synchronous high reset.if (cnt < fifo_size)creg[cnt+1] = ffinif (cnt not equal to 0)creg[cnt] = creg[cnt-1]Table 9-3. First In First Out Truth Table — Synchronous High Resetwena rena clk_en clk rst cnt creg- - 0 - - cnt creg- - 1 posedge 1 0 creg-1 - 1 posedge 0 if (cnt < fifo_size)cnt+10 1 1 posedge 0 if (cnt not equal to 0)cnt -1if (cnt < fifo_size)creg[cnt+1] = ffinif (cnt not equal to 0)creg[cnt] = creg[cnt-1]ffoutaemptyafullemptyfull= creg[0]= (cnt ≤ aempty_size)= (cnt ≥ afull_size)= (cnt = 0)= (cnt = fifo_size)210ModuleWare Reference Manual, Library Version 1.9September 18, 2008