ModuleWare Reference Guide - Hornad

Serial to Parallel Shifter (shiftsp)Sequential PartsSerial to Parallel Shifter (shiftsp)This part allows you to load data bits (scalar input port din) into theshift register and shift out this data one word at a time. The resultantword is placed in the output port dout. The number of internal flipflopsused is equal to the width of the output data port dout. A newvalue can be loaded into the internal register by the reset operation.The reset operation has the highest priority compared to the shiftoperation.A shift operation takes place on the internal register in the absence ofa load operation. During the shift operation the internal register isshifted by 1.The direction of the shift is decided by the scalar input port rl. If port rl is activated, the shiftright by 1 operation is executed. If port rl is deactivated, a shift left by 1 operation is executed.In both cases, port din is shifted into the new bit. For right shift by 1 operation, port din is themost MSB while for left shift by 1 operation, port din is the LSB. The polarity of port rl iscontrolled by the enumerated parameter rl_type (ActiveHigh, ActiveLow). The port rl isconsidered activated if its value is 1 and the polarity is ActiveHigh or its value is 0 and thepolarity is ActiveLow.The part can be triggered on the rising edge or the falling edge of port clk. The polarity of portclk is controlled by the enumerated parameter clk_type (Rising, Falling). Note that RisingLast,FallingLast, RisingEdge and FallingEdge are also supported for VHDL.The clk can optionally be enabled by the scalar input port clk_en. The polarity of port clk_en iscontrolled by enumerated parameter clk_en_type (ActiveHigh, ActiveLow). Do not change thevalue of the parameter clk_en_type if the clk_en port is not used.The register can be reset to the value of the parameter rst_val by activating the scalar input portrst. The mode of the rst is controlled by the enumerated parameter rst_type (SyncActiveHigh,AsyncActiveHigh, SyncActiveLow, AsyncActiveLow. If the input ports clk and rst (forasynchronous behavior) are not enabled, the internal register retains its value.This part is equivalent to a shift register. This part has n flip-flops and shifter logic as per theshift operations (where n is the width of the output port dout). Based on the parameterized state,the performance of the shift register can be accurately estimated.If clk_en is not connected, it is driven by 1. If the clock enable feature is not used, the scalarinput port clk_en must be unconnected and the parameter clk_en_type must be set toActiveHigh. Port clk_en can also be driven by an active driver, in which case the clk_en_typemust be correctly adjusted. The HDL code for clk_en is optimized away if it is not used.Parameter rst_val can take LNBF format as described in the Constant Value (constval) model.ModuleWare Reference Manual, Library Version 1.9 199September 18, 2008