ModuleWare Reference Guide - Hornad

Synthesizable Single-Port RAM (ramsp)Memory PartsSynthesizable Single-Port RAM (ramsp)This part implements a synthesizable single-port Random AccessMemory (RAM) with separate read din and write dout data portssynchronized to the same clockThe size of the RAM is specified by the address_width anddata_width parameters.The width of address port addr must be equal to the address_widthparameter. If the address_width parameter is empty, then the size ofthe RAM is determined from the width of addr port.The width of input port din must be equal to or greater than the data_width parameter. If thedata_width parameter is empty, then the size of the RAM is determined from the width of thedin port.The RAM can be initialized using the initial_value parameter which must be a valid LNBFstring. All locations of the RAM will have the same initial value defined in the initial_valueparameter.The RAM has write and read operations. The write operation takes place if the scalar input portwe is enabled (we = 1). The read operation takes place if the scalar input port we is disabled (we= 0). In a write operation, the value of the input bus din is written to the address locationspecified by the value of the input bus addr. In a read operation, the value in the addresslocation specified by addr is placed on the output port dout.The enumerated parameters clk_type (Rising, Falling, RisingLast, FallingLast, RisingEdge,FallingEdge) and we_type (ActiveHigh, ActiveLow) control which clock edge is used for theread and write operations.(Note that RisingLast, FallingLast, RisingEdge and FallingEdge are supported for VHDL only.)This part can be synthesized using Altera or Xilinx technologies.ParametersTable 9-12. Synthesizable Single-Port RAM ParametersParameter Values Defaultdin, doutaddrclk_typewe_typeaddress_widthdata_widthinitial_valuePort widths (must be > 0)Port widths (must be > 0)Rising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh, ActiveLowWidth of the addressable memoryWidth of the RAM dataInitial value of RAMAutomaticAutomaticRisingActiveHigh30Design Rule Checks• An error is issued if the width of any port cannot be determined, if any of ports clk and wedo not have a fixed width of 1, if ports din and dout do not have the same width, if the widthModuleWare Reference Manual, Library Version 1.9 227September 18, 2008