ModuleWare Reference Guide - Hornad

ParametersRegister PartsT Flip-Flop (tff)Table 7-31. T Flip-Flop Truth Table — Synchronous rst and set (cont.)enable clk rst set q qb- posedge 1 0 / NC rst_val NOT(rst_val)- posedge 0 / NC 1 set_val NOT(set_val)NC posedge 0 / NC 0 / NC T TT NOT(T TT)0 posedge 0 / NC 0 / NC q qb1 posedge 0 / NC 0 / NC T TT NOT(T TT)Table 7-32. T Flip-Flop ParametersParameter Values Defaultq, qb Port widths (must be > 0) Automaticclk_typeenable_typeqb_typerst_typeset_typeinitializationrst_valset_valRising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeActiveHigh,ActiveLow,NoneEnabled,DisabledAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneAsyncActiveHigh,SyncActiveHigh,AsyncActiveLow,SyncActiveLow,NoneEnabled,DisabledRegister reset value (must be >= 0)Register set value (must be >= 0)RisingActiveHighEnabledAsyncActiveHighAsyncActiveHighDisabled01Design Rule Checks• An error is issued if the width of any port cannot be determined or if ports clk, enable, rstand set do not have a fixed width of 1.• A warning is issued and HDL generation fails for this part if port clk is not connected or if atleast one of ports q and qb are not connected.ModuleWare Reference Manual, Library Version 1.9 163September 18, 2008