ModuleWare Reference Guide - Hornad

Memory PartsROM (rom)The corresponding code for Verilog is:case(addr)0:mem[0] = 8’b11100011; -- e31:mem[1] = 8’b10100000; -- a02:mem[2] = 8’b10100000; -- a0......15:mem[15] = 8’b00101110; -- 2edefault:mem[n] = 8’bx;endcaseFunctionromtable is the table of values created from the ROM file.dout = romtable(addr) ifaddr < rom_sizeParametersTable 9-7. ROM ParametersParameter Values Defaultaddrdoutclk_typeendian_moderom_filePort width (must be > 0)Port width (must be > 0)Rising,Falling,RisingLast,FallingLast,RisingEdge,FallingEdgeLiitleEndian, BigEndianPathname of file used to initialize the ROMAutomaticAutomaticRisingLiitleEndiannullDesign Rule Checks• An error is issued if the width of any port cannot be determined, if port clk does not have afixed width of 1, if the rom_file parameter is empty, if the width of dout is not 8 bits, if theIntel HEX file does not end with an end-of-file (EOF) record or if any record in the fileviolates the syntax for Intel Hex files.• An error is also issued if the addr port width decodes to a number of locations less than theIntel HEX records. In this case, the generation is halted and a message suggests theminimum required address width. For example, if a 3 bit address has been used (decodes to8 locations) but the HEX file contains 16 address locations, the message suggests having anaddress width of at least 4 bits.• A warning is issued and HDL generation fails for this part if any of ports addr, clk or doutare not connected.• A warning is issued if the addr port width decodes to a number of locations greater than theIntel HEX records but the HDL generation continues.Hexadecimal File Format (Intel Hex)An Intel HEX file is an ASCII description of a binary file. Each line in the file contains a HEXrecord.The file must end with an EOF record of the form:218ModuleWare Reference Manual, Library Version 1.9September 18, 2008