Design and Verification of Adaptive Cache Coherence Protocols ...

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that the message queues all become empty in a drained term. Thiscanbeproved according to Lemma 15, which guarantees that a Cache, WbAck, FlushAck or Wb message can be consumed at the cache, and a Purge message can be consumed at the memory. Lemma 20 Given a WP term s, (1) Pmb id(s) = Pmb id(dr(s)) (2) Mpb id(s) = Mpb id(dr(s)) (3) Proc id(s) = Proc id(dr(s)) Lemma 21 Given a WP term s, (1) Min(dr(s)) = (2) Mout(dr(s)) = (3) Cin id(dr(s)) = (4) Cout id(dr(s)) = The draining rules have no impact on the value of a memory cell. Acache cell in a stable state remains una ected. An uncached address remains uncached provided that no Cache message is drained. Lemma 22 captures these properties. Lemma 22 Given a WP term s, (1) Cell(a,v,T[-,-]) 2 Mem(s) ) Cell(a,v,T[-, ]) 2 Mem(dr(s)) (2) Cell(a,v,Clean) 2 Cache id(s) ) Cell(a,v,Clean) 2 Cache id(dr(s)) (3) Cell(a,v,Dirty) 2 Cache id(s) ) Cell(a,v,Dirty) 2 Cache id (dr(s)) (4) a =2 Cache id(s) ^ Msg(H,id ,Cache,a,-) =2 MoutCin id(s1) ) a =2 Cache id(dr(s)) Lemma 23 ensures that in a drained term, an address will be cached in the Clean state if a Cache or WbAck message is drained an address will be cached in the Dirty state if a Wb message is drained an address will be uncached if a Purge or FlushAck message is drained. The proof follows from Lemma 15 and the draining rules (note that messages can be drained in any order because of the con uence of the draining rules). Lemma 23 Given a WP term s, (1) Msg(H,id ,Cache,a,v) 2 MoutCin id (s) ) Cell(a,v,Clean) 2 Cache id(dr(s)) (2) Msg(id ,H,Purge,a) 2 MinCout id(s) ) a =2 Cache id(dr(s)) (3) Msg(id ,H,Wb,a,v) 2 MinCout id (s) ) Cell(a,v,Dirty) 2 Cache id(dr(s)) (4) Cell(a,v,T[-,(id ,v)j-]) 2 Mem(s) ) Cell(a,v,Dirty) 2 Cache id(dr(s)) (5) Msg(H,id ,WbAck,a) 2 MoutCin id (s) ) Cell(a,v,Clean) 2 Cache id(dr(s)) (6) Msg(H,id ,FlushAck,a) 2 MoutCin id (s) ^ Msg(H,id ,Cache,a,-) =2 MoutCin id(s) ) a =2 Cache id(dr(s)) De nition 24 (Mapping from WP to CRF) Given a WP term s, the corresponding CRF term f(s) is the drained term dr(s) with all message queues and cache identi ers removed. It is obvious that the mapping function maps the initial WP term (with all caches and network queues empty) to the initial CRF term (with all semantic caches empty). For any WP term, the mapping function guarantees that it is mapped to a legal CRF term (this follows trivially from the simulation theorem given below). 100
5.4.3 Simulation of WP in CRF Theorem 25 (CRF Simulates WP) Given WP terms s1 and s2, s1 ! s2 in WP ) f(s1) ! f(s2) in CRF Proof The proof is based on a case analysis on the imperative ruleusedin the rewriting of `s1 ! s2' in WP. Let a be the address and id the cache identi er. Imperative Processor Rules If Rule IP1 (Loadl-on-Clean) applies, then Cell(a,v,Clean) 2 Cache id(s1) ^ Cell(a,v,Clean) 2 Cache id(s2) ) Cell(a,v,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Loadl ) If Rule IP2 (Loadl-on-Dirty) applies, then Cell(a,v,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,v,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id (dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Loadl ) If Rule IP3 (Storel-on-Clean) applies, then Cell(a,-,Clean) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id(dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Storel ) If Rule IP4 (Storel-on-Dirty) applies, then Cell(a,-,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id(dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Storel ) If Rule IP5 (Commit-on-Clean) applies, then Cell(a,v,Clean) 2 Cache id(s1) ^ Cell(a,v,Clean) 2 Cache id(s2) ) Cell(a,v,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Commit ) If Rule IP6 (Commit-on-Invalid) applies, and if Msg(H,id ,Cache,a,-) =2 MoutCin id(s1), then a =2 Cache id(s1) ^ a =2 Cache id(s2) ) a =2 Cache id(dr(s1)) ^ a =2 Cache id(dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Commit ) If Rule IP6 (Commit-on-Invalid) applies, and if Msg(H,id ,Cache,a,v) 2 MoutCin id (s1), then a =2 Cache id(s1) ^ a =2 Cache id(s2) ) Cell(a,v,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemma 23 ) ) f(s1) ! f(s2) (CRF-Commit ) If Rule IP7 (Reconcile-on-Dirty) applies, then Cell(a,v,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,v,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id (dr(s2)) (Lemma 22 ) ) f(s1) ! f(s2) (CRF-Reconcile ) 101
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101: Backward-Message-Cache-to-Mem-for-W
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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