Processor Rules Rule Name Instruction Cstate Action Next Cstate GCRF-Loadl Loadl(a) Cell(a,v,cs) retire Cell(a,v,cs) GCRF-Storel Storel(a,v) Cell(a,-,-) retire Cell(a,v,S) GCRF-Commit Commit(a) Cell(a,v, ) retire Cell(a,v, ) a =2 sache retire a =2 sache GCRF-Reconcile Reconcile(a) Cell(a,v,cs) (cs 6= ) retire Cell(a,v,cs) a =2 sache retire a =2 sache Background Rules Rule Name Cstate Mstate Next Cstate Next Mstate GCRF-<strong>Cache</strong> a =2 sache Cell(a,v) Cell(a,v, ) Cell(a,v) GCRF-Writeback Cell(a,v,id jcs) Cell(a,-) Cell(a,v,cs) Cell(a,v) GCRF-Purge Cell(a,-, ) Cell(a,v) a =2 sache Cell(a,v) GCRF-Writeback Rule Figure 3.8: Summary <strong>of</strong> GCRF Rules (except reordering rules) Site(id , mem, Cell(a,v,id jcs) j sache, pmb, mpb, proc) ! Site(id , mem[a:=v], Cell(a,v,cs) j sache, pmb, mpb, proc) Site(id , mem, Cell(a,v,id1jcs) j sache, pmb, mpb, proc) j Site(id1, mem1, sache1, pmb1, mpb1, proc1) ! Site(id , mem, Cell(a,v,cs) j sache, pmb, mpb, proc) j Site(id1, mem1[a:=v], sache1, pmb1, mpb1, proc1) GCRF-Purge Rule Site(id , mem, Cell(a,-, ) j sache, pmb, mpb, proc) ! Site(id , mem, sache, pmb, mpb, proc) The GCRF model also allows instructions to be reordered the reordering rules <strong>of</strong> CRF all remain unchanged. The GCRF rules are summarized in Figure 3.8. In the tabular description, for the cache <strong>and</strong> purge rules, the memory state re ects the memory cell in the same site as the sache cell for the writeback rule, the memory state re ects the memory cell in site id . The GCRF model also allows instructions to be reordered the reordering rules are exactly thesameasthose <strong>of</strong> CRF. In addition, we can de ne a new commit instruction that commits an address with respect to an individual memory. The semantics <strong>of</strong> the instruction can be speci ed as follows: Site(id , mem, sache, ht,Commit(a,id )ipmb, mpb, proc) if Cell(a,-,id j-) =2 sache ! Site(id , mem, sache, pmb, mpbjht,Acki, proc) The Commit(a,id ) instruction guarantees that the dirty copy is written back to the memory at site id before the instruction completes. The normal commit instruction can be de ned by a sequence <strong>of</strong> the ner-grain commit instructions. 64
Chapter 4 The Base <strong>Cache</strong> <strong>Coherence</strong> Protocol The Base protocol is the most straightforward implementation <strong>of</strong> the CRF model. An attractive characteristic <strong>of</strong> Base is its simplicity: no state needs to be maintained at the memory side. In Base, a commit operation on a dirty cell forces the data to be written back to the memory, <strong>and</strong> a reconcile operation on a clean cell forces the data to be purged from the cache. This is ideal for programs in which only necessary commit <strong>and</strong> reconcile operations are performed. In this chapter, we rst present a novel protocol design methodology called Imperative-&- Directive that will be used throughout this thesis. Section 4.2 describes the system con guration <strong>of</strong> the Base protocol <strong>and</strong> gives the message passing rules for non-FIFO <strong>and</strong> FIFO networks. We de ne the imperative rules <strong>of</strong> Base in Section 4.3, <strong>and</strong> present the complete Base protocol in Section 4.4. Section 4.5 proves the soundness <strong>of</strong> Base by showing that the imperative Base rules can be simulated in CRF Section 4.6 proves the liveness <strong>of</strong> Base by showing that each processor can always make progress (that is, a memory instruction can always be completed eventually). 4.1 The Imperative-&-Directive <strong>Design</strong> Methodology In spite <strong>of</strong> the development <strong>of</strong> various cache coherence protocols, it is di cult to discern any methodology that has guided the design <strong>of</strong> existing protocols. A major source <strong>of</strong> complexity in protocol design is that the designer <strong>of</strong>ten deals with many di erent issues simultaneously. Are coherence states being maintained correctly? Is it possible that a cache miss may never be serviced? What is the consequence if messages get reordered in the network? How to achieve better adaptivity for programs with di erent access patterns? Answering such questions can be di cult for sophisticated protocols with various optimizations. The net result is that protocol design is viewed as an enigma, <strong>and</strong> even the designer is not totally con dent <strong>of</strong> his or her underst<strong>and</strong>ing <strong>of</strong> the protocol behavior. We propose a two-stage design methodology called Imperative-&-Directive that separates soundness <strong>and</strong> liveness concerns in the design process (see Figure 4.1). Soundness ensures that 65
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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Mandatory Processor Rules Instructi
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CacheReq message. In the latter cas
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New