Design and Verification of Adaptive Cache Coherence Protocols ...

can be classi ed into two non-overlapping sets: mandatory rules and voluntary rules. The
distinction between mandatory rules and voluntary rules is that mandatory rules require at
least weak fairness to ensure the liveness of the system, while voluntary rules have no such
requirement and are provided purely for adaptivity and performance reason. Intuitively, an
enabled mandatory rule must be applied eventually, while an enabled voluntary rule may or
may not be applied eventually.
The fairness requirement of mandatory rules can be expressed in terms of weak fairness and
strong fairness. Weak fairness means that if a mandatory rule can be applied, it will be applied
eventually or become impossible to apply at some later time. Strong fairness means that if
a mandatory rule can be applied, it will be applied eventually or become impossible to apply
forever. When we say a rule is weakly or strongly fair, we mean the application of the rule on
each redex is weakly or strongly fair.
A mandatory action is usually enabled by events such as an instruction from the processor
or a message from the network. Avoluntary action, in contrast, can be enabled as long as the
cache or memory cell is in some appropriate state. For example, a mandatory writeback rule
requires a cache to write a dirty copy back to the memory once a writeback request is received,
while a voluntary writeback rule allows the same operation as long as the cache state of the
address shows that the data has been modi ed.
Conventional cache coherence protocols consist of only mandatory actions. Our view of an
adaptive coherence protocol consists of three components, mandatory rules, voluntary rules and
heuristic policies. The existence of voluntary rules provides enormous adaptivity that can be
exploited via various heuristic policies. A heuristic mechanism can use heuristic messages and
heuristic states to help determine when a voluntary rule should be invoked. Di erent heuristic
policies can result in di erent performance, but the soundness and liveness of the system are
always guaranteed.
4.2 The Message Passing Rules
Figure 4.2 de nes the system con guration of Base. The system contains a memory site and a
set of cache sites. The memory site has three components, a memory, an incoming queue and an
outgoing queue. Each cache site contains an identi er, a cache, an incoming queue, an outgoing
queue and a processor. Although the memory site appears as one component syntactically,
it can be distributed among multiple sites in DSM systems. Initially all caches and message
queues are empty.
A message queue is a sequence of messages. We use ` ' and ` ' as the constructor for
incoming and outgoing queues, respectively. Each message has several elds: a source, a desti-
nation, a command, an address and an optional data. The source and destination can be either
a cache site or the home memory (represented by `H'). Given a message msg, we use notations
Src(msg), Dest(msg), Cmd(msg) and Addr(msg) to represent its source, destination, command
and address.
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