Design and Verification of Adaptive Cache Coherence Protocols ...

CRF model has both upward and downward compatibility, that is, the ability to run existing
programs correctly and e ciently on a CRF machine, and the ability to run CRF programs
well on existing machines.
The CRF model was motivated from a directory-based cache coherence protocol that was
originally designed for the MIT Start-Voyager multiprocessor system [11, 12]. The protocol
veri cation requires a memory model that speci es the legal memory behaviors that the protocol
was supposed to implement. Ironically, we did not have such a speci cation even after the
protocol design was completed. As a result, it was not clear what invariants must be proved
in order to ensure that the cache coherence protocol always exhibits the same behavior as
sequential consistency for properly synchronized programs. The lack of a precise speci cation
also made it di cult to understand and reason about the system behavior for programs that
may have data races. To deal with this dilemma, we transformed the protocol by eliminating
various directive operations and implementation details such as message queues, preserving the
semantics throughout the transformation. This eventually led to CRF, an abstract protocol
that cannot be further simpli ed. The CRF model can be implemented e ciently for shared
memory systems, largely because the model itself is an abstraction of a highly optimized cache
coherence protocol.
We have designed a set of adaptive cache coherence protocols which are optimized for some
common access patterns. The Base protocol is the most straightforward implementation of
CRF, and is ideal for programs in which only necessary commit and reconcile operations are
performed. The WP protocol allows a reconcile operation on a clean cache cell to complete
without purging the cell so that the data can be accessed by subsequent load operations without
causing a cache miss this is intended for programs that contain excessive reconcile operations.
The Migratory protocol allows an address to be cachedinatmostonecache it ts well when
one processor is likely to access an address many times before another processor accesses the
same address.
We further developed an adaptive cache coherence protocol called Cachet that provides
a wide scope of adaptivity for DSM systems. The Cachet protocol is a seamless integration
of multiple micro-protocols, and embodies both intra-protocol and inter-protocol adaptivity
to achieve high performance under changing memory access patterns. A cache cell can be
modi ed without the so-called exclusive ownership, which e ectively allows multiple writers
for the same memory location simultaneously. This can reduce the average latency for write
operations and alleviate potential cache thrashing due to false sharing. Moreover, the purge
of an invalidated cache cell can be deferred to the next reconcile point, which can help reduce
cache thrashing due to read-write false sharing. An early version of Cachet with only the Base
and WP micro-protocols can be found elsewhere [113]. Since Cachet implements the CRF
model, it is automatically a protocol that implements the memory models whose programs can
be translated into CRF programs.
Our view of adaptive protocols contains three layers: mandatory rules, voluntary rules
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