Design and Verification of Adaptive Cache Coherence Protocols ...

More documents

Recommendations

Info

[115] R. T. Simoni. Cache Coherence Directories for Scalable Multiprocessors. PhD Dissertation, Stanford University, Mar. 1995. [116] J. P. Singh, W.-D. Weber, and A. Gupta. SPLASH: Stanford Parallel Applications for Shared-Memory. Computer Architecture News, 20(1):5{44. [117] R. L. Sites and R. T. Witek, editors. Alpha AXP Architecture Reference Manual. Butterworth-Heinemann, 1995. [118] I. C. Society. IEEE Standard for Scalable Coherent Interface. 1993. [119] P. Stenstrom, B. Brorsson, and L. Sandberg. An Adaptive Cache Coherence Protocol Optimized for Migratory Sharing. In Proceedings of the 20th International Symposium on Computer Architecture, May 1993. [120] U. Stern and D. L. Dill. Automatic Veri cation of the SCI Cache Coherence Protocol. In Correct Hardware Design and Veri cation Methods: IFIP WG10.5 Advanced Research Working Conference Proceedings, 1995. [121] D. L. Weaver and T. Germond, editors. The SPARC Architecture Manual (Version 9). Prentice-Hall, 1994. [122] W. D. Weber and A. Gupta. Analysis of Cache Invalidation Patterns in Multiprocessors. In Proceedings of the 3rd International Conference on Architectural Support for Programming Languages and Operating Systems, 1989. [123] P. J. Windley. Formal Modeling and Veri cation of Microprocessors. IEEE Transactions on Computers, 44(1), Jan. 1995. [124] S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta. The SPLASH-2 Programs: Characterization and Methodological Considerations. In Proceedings of the 22nd International Symposium on Computer Architecture, June 1995. [125] K. C. Yeager. The MIPS R10000 Superscalar Microprocessor. IEEE Micro, pages 28{40, Apr. 1996. [126] D. Yeung, J. Kubiatowicz, and A. Agarwal. MGS: A Multigrain Shared Memory System. In Proceedings of the 23rd International Symposium on Computer Architecture, 1996. 178
Page 1:
CSAIL Computer Science and Artifici
Page 5:
Design and Veri cation of Adaptive
Page 8 and 9:
I am truly grateful to my parents f
Page 10 and 11:
4 The Base Cache Coherence Protocol
Page 13 and 14:
List of Figures 1.1 Impact of Archi
Page 15 and 16:
Chapter 1 Introduction Shared memor
Page 17 and 18:
transparent and exposed only for lo
Page 19 and 20:
Example 1: Can both registers r1 an
Page 21 and 22:
and release locks, which guard ever
Page 23 and 24:
that are interconnected with an o -
Page 25 and 26:
although various techniques have be
Page 27 and 28:
y showing that each processor can a
Page 29 and 30:
s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32:
Program counter (pc) +1 Instruction
Page 33 and 34:
Branch target buffer (btb) Program
Page 35 and 36:
instruction is waiting to be dispat
Page 37 and 38:
Current State: Proc(ia, rf , rob, b
Page 39 and 40:
Rule Name mem pmb mpb Next mem Next
Page 41 and 42:
Specification Implementation t 1 B
Page 43 and 44:
Intuitively, \2P " means that \P is
Page 45 and 46:
(a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48:
ewritten to s2 according to rule R.
Page 49 and 50:
It can be shown that the relaxed di
Page 51 and 52:
Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54:
Producer Storel(a,v) Commit(a) Cons
Page 55 and 56:
Commit/Reconcile Purge Loadl/Commit
Page 57 and 58:
instructions, because of the lack o
Page 59 and 60:
CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62:
3.4 Universality of the CRF Model M
Page 63 and 64:
Translation from CRF to PSO: The Fe
Page 65 and 66:
proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68:
Chapter 4 The Base Cache Coherence
Page 69 and 70:
can be classi ed into two non-overl
Page 71 and 72:
arbitrarily in an outgoing queue (t
Page 73 and 74:
4.3 The Imperative Rules of the Bas
Page 75 and 76:
Imperative Processor Rules Instruct
Page 77 and 78:
Figure 4.5 de nes the rules of the
Page 79 and 80:
4.5.2 Mapping from Base to CRF We d
Page 81 and 82:
Base Imperative Rule CRF Rule IP1 (
Page 83 and 84:
Base Rule Base Imperative Rule P1 I
Page 85 and 86:
eceives a CacheReq message, it will
Page 87 and 88:
e completed if it has an in nite nu
Page 89 and 90:
SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92:
Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94:
message can be resumed eventually.
Page 95 and 96:
If the memory state shows that the
Page 97 and 98:
5.3.3 FIFO Message Passing The live
Page 99 and 100:
Figure 5.7 gives the M-engine rules
Page 101 and 102:
Backward-Message-Cache-to-Mem-for-W
Page 103 and 104:
5.4.3 Simulation of WP in CRF Theor
Page 105 and 106:
WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108:
WP Rule WP Imperative & Directive R
Page 109 and 110:
(4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112:
This completes the proof according
Page 113 and 114:
emains as CachePending, there mustb
Page 115 and 116:
M-engine Rules Msg from id Mstate A
Page 117 and 118:
Chapter 6 The Migratory Cache Coher
Page 119 and 120:
Commit/Reconcile Send Purge Loadl/C
Page 121 and 122:
Mandatory Processor Rules Instructi
Page 123 and 124:
while the memory sends a FlushReq m
Page 125 and 126:
Lemma 38 D is strongly terminating
Page 127 and 128:
Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147 and 148: Composite Imperative C-engine Rules
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179: [101] F. Pong and M. Dubois. A New
show all

Design and Verification of Adaptive Cache Coherence Protocols ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?