Design and Verification of Adaptive Cache Coherence Protocols ...

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If Rule IP2 (Loadl-on-Dirty) applies, then Cell(a,v,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,v,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id (dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Loadl ) If Rule IP3 (Storel-on-Clean) applies, then Cell(a,-,Clean) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Storel ) If Rule IP4 (Storel-on-Dirty) applies, then Cell(a,-,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,-,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Storel ) If Rule IP5 (Commit-on-Clean) applies, then Cell(a,v,Clean) 2 Cache id(s1) ^ Cell(a,v,Clean) 2 Cache id(s2) ) Cell(a,v,Clean) 2 Cache id(dr(s1)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Commit ) If Rule IP6 (Commit-on-Invalid) applies, then a =2 Cache id(s1) ^ a =2 Cache id(s2) ) a =2 Cache id(dr(s1)) ^ a =2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Commit ) If Rule IP7 (Reconcile-on-Dirty) applies, then Cell(a,v,Dirty) 2 Cache id(s1) ^ Cell(a,v,Dirty) 2 Cache id(s2) ) Cell(a,v,Dirty) 2 Cache id(dr(s1)) ^ Cell(a,v,Dirty) 2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Reconcile ) If Rule IP8 (Reconcile-on-Invalid) applies, then a =2 Cache id(s1) ^ a =2 Cache id(s2) ) a =2 Cache id(dr(s1)) ^ a =2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Reconcile ) Imperative C-engine Rules If Rule IC1 (C-Purge) applies, then Cell(a,-,Clean) 2 Cache id(s1) ^ a =2 Cache id(s2) ) Cell(a,-,Clean) 2 Cache id(dr(s1)) ^ a =2 Cache id(dr(s2)) (Lemma 7 ) ) f(s1) ! f(s2) (CRF-Purge ) Imperative M-engine Rules 80
Base Rule Base Imperative Rule P1 IP1 (Loadl-on-Clean) P2 IP2 (Loadl-on-Dirty) P3 P4 P5 IC3 (C-Send-CacheReq) P6 IP3 (Storel-on-Clean) P7 IP4 (Storel-on-Dirty) P8 P9 P10 IC3 (C-Send-CacheReq) P11 IP5 (Commit-on-Clean) P12 IC2 (C-Send-Wb) P13 P14 P15 IP6 (Commit-on-Invalid) P16 IC1 (C-Purge) P17 IP7 (Reconcile-on-Dirty) P18 P19 P20 IP8 (Reconcile-on-Invalid) VC1 IC1 (C-Purge) VC2 IC2 (C-Send-Wb) VC3 IC3 (C-Send-CacheReq) MC1 IC4 (C-Receive-Cache) MC2 IC5 (C-Receive-WbAck) MM1 IM1 (M-Receive-CacheReq-&-Send-Cache) MM2 IM2 (M-Receive-Wb-&-Send-WbAck) Figure 4.7: Derivation of Base from Imperative Rules If Rule IM1 (M-Receive-CacheReq-&-Send-Cache) applies, then Cell(a,v) 2 Mem(s1) ^ Msg(id ,H,CacheReq,a) 2 Min(s1) ^ Cell(a,v) 2 Mem(s2) ^ Msg(H,id ,Cache,a,v) 2 Mout(s2) ) Cell(a,v) 2 Mem(dr(s1)) ^ a =2 Cache id(dr(s1)) ^ (Lemmas 5 & 8 ) Cell(a,v) 2 Mem(dr(s2)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemmas 5 & 8 ) ) f(s1) ! f(s2) (CRF-Cache ) If Rule IM2 (M-Receive-Wb-&-Send-WbAck) applies, then Msg(id ,H,Wb,a,v) 2 Min(s1) ^ Cell(a,v) 2 Mem(s2) ^ Msg(H,id ,WbAck,a) 2 Mout(s2) ) Cell(a,v,Dirty) 2 Cache id(dr(s1)) ^ (Lemma 8 ) Cell(a,v) 2 Mem(dr(s2)) ^ Cell(a,v,Clean) 2 Cache id(dr(s2)) (Lemmas 5 & 8 ) ) f(s1) ! f(s2) (CRF-Writeback ) Draining Rules If Rule IC2 (C-Send-Wb), IC3 (C-Send-CacheReq), IC4 (C-Receive-Cache), IC5 (C-Receive- WbAck), Message-Cache-to-Mem or Message-Mem-to-Cache applies, then f(s1) =f(s2) (Since the rule or its backward version is a draining rule) Figure 4.6 summarizes the simulation proof. 2 81
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81: Base Imperative Rule CRF Rule IP1 (
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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