Design and Verification of Adaptive Cache Coherence Protocols ...

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From Memory to Cache From Cache to Memory Imperative Messages Msg(H,id ,Cache,a,v) Msg(id ,H,Purge,a) Msg(H,id ,WbAck,a) Msg(id ,H,Wb,a,v) Msg(H,id ,FlushAck,a) Directive Messages Msg(H,id ,PurgeReq,a) Msg(id ,H,CacheReq,a) Figure 5.2: Protocol Messages of WP Purge: the cache informs the memory of a purge operation. Wb: the cache writes a dirty copy back tothememory. CacheReq: the cache requests a data copy from the memory. 5.2 The Imperative Rules of the WP Protocol We develop a set of imperative rules that specify all coherence actions that determine the soundness of the system. This includes three sets of rules, the processor rules, the cache engine rules and the memory engine rules. Processor Rules: The imperative processor rules of WP contain all the imperative processor rules of Base (see Section 4.3), and the Reconcile-on-Clean rule that allows a Reconcile instruction to complete even when the address is cached in the Clean state. Reconcile-on-Clean Rule Site(id , Cell(a,v,Clean) j cache, in, out, ht,Reconcile(a)ipmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpbjht,Acki, proc) C-engine Rules: Acache can purge a clean cell and inform the memory via a Purge message. It can also write the data of a dirty cell to the memory via a Wb message and set the cache state to WbPending, indicating that a writeback operation is being performed on the address. There are two possible acknowledgments for a writeback operation. If a writeback acknowledgment (WbAck) is received, the cache state becomes Clean if a ush acknowledgment (FlushAck) is received, the cache state becomes Invalid (that is, the address is purged from the cache). When a cache receives a Cache message, it simply caches the data in the Clean state. Unlike Base, a cache can receive a data copy from the memory even though it has not requested for the data. Figure 5.3 shows cache state transitions due to imperative operations. C-Send-Purge Rule Site(id , Cell(a,-,Clean) j cache, in, out, pmb, mpb, proc) ! Site(id , cache, in, out Msg(id ,H,Purge,a), pmb, mpb, proc) C-Send-Wb Rule Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpb, proc) ! Site(id , Cell(a,v,WbPending) j cache, in, out Msg(id ,H,Wb,a,v), pmb, mpb, proc) 88
Commit/Reconcile C-Receive-WbAck Rule Loadl/Commit/Reconcile Storel Loadl/Storel/Reconcile Invalid Send Purge Receive Cache Clean Receive WbAck Wb- Pending Send Wb Dirty Receive FlushAck Figure 5.3: Cache State Transitions of WP's Imperative Operations Site(id , Cell(a,v,WbPending) j cache, Msg(H,id ,WbAck,a) in, out, pmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpb, proc) C-Receive-FlushAck Rule Site(id , Cell(a,-,WbPending) j cache, Msg(H,id ,FlushAck,a) in, out, pmb, mpb, proc) ! Site(id , cache, in, out, pmb, mpb, proc) C-Receive-Cache Rule Site(id , cache, Msg(H,id ,Cache,a,v) in, out, pmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpb, proc) M-engine Rules: The memory can send a data copy of an address to a cache in which the directory shows the address is not cached the directory is updated accordingly. When the memory receives a purge message, it simply deletes the cache identi er from the directory. When the memory receives a writeback message, it suspends the message and removes the corresponding cache identi er from the directory. A suspended writeback message can be resumed if the directory shows that the address is not cached in any cache. In this case, the memory updates its value and sends a ush acknowledgment back to the cache site. If the writeback message is the only suspended message, the memory can send a writeback acknowledgment instead of a ush acknowledgment toallowthecache to retain a clean copy. M-Send-Cache Rule Msite(Cell(a,v,T[dir, ]) j mem, in, out) if id =2 dir ! Msite(Cell(a,v,T[id jdir, ]) j mem, in, out Msg(H,id ,Cache,a,v)) M-Receive-Purge Rule Msite(Cell(a,v,T[id jdir,sm]) j mem, Msg(id ,H,Purge,a) in, out) ! Msite(Cell(a,v,T[dir,sm]) j mem, in, out) M-Receive-Wb Rule Msite(Cell(a,v1,T[id jdir,sm]) j mem, Msg(id ,H,Wb,a,v) in, out) ! Msite(Cell(a,v1,T[dir,smj(id ,v)]) j mem, in, out) M-Send-FlushAck Rule Msite(Cell(a,-,T[ ,(id ,v)jsm]) j mem, in, out) ! Msite(Cell(a,v,T[ ,sm]) j mem, in, out Msg(H,id ,FlushAck,a)) 89
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89: SYS Sys(MSITE, SITEs) System MSITE
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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