Design and Verification of Adaptive Cache Coherence Protocols ...

transparent and exposed only for low-level memory-mapped input and output operations. For
multiprocessor systems, however, these features are anything but transparent. Indeed, a whole
area of research has evolved around what view of memory should be presented to the program-
mer, the compiler writer, and the computer architect.
The essence of memory models is the correspondence between each load instruction and the
store instruction that supplies the data retrieved by the load. The memory model of uniproces-
sor systems is intuitive: a load operation returns the most recent value written to the address,
and a store operation binds the value for subsequent load operations. In parallel systems, no-
tions such as \the most recent value" can become ambiguous since multiple processors access
memory concurrently. Therefore, it can be di cult to specify the resulting memory model
precisely at the architecture level [33, 36, 97]. Surveys of some well-known memory models can
be found elsewhere [1, 66].
Memory models can be generally categorized as architecture-oriented and program-oriented.
One can think of an architecture-oriented model as the low-level interface between the compiler
and the underlying architecture, while a program-oriented model the high-level interface be-
tween the compiler and the program. Many architecture-oriented memory models [61, 86, 117,
121] are direct consequences of microarchitecture optimizations such as write-bu ers and non-
blocking caches. Every programming language has a high-level memory model [19, 56, 54, 92],
regardless of whether it is described explicitly or not. The compiler ensures that the semantics
of a program is preserved when its compiled version is executed on an architecture with some
low-level memory model.
1.1.1 Sequential Consistency
Sequential consistency [72] has been the dominant memory model in parallel computing for
decades due to its simplicity. A system is sequentially consistent if the result of any execution
is the same as if the operations of all the processors were executed in some sequential order,
and the operations of each individual processor appear in this sequence in the order speci ed
by its program. Sequential consistency requires that memory accesses be performed in-order
on each processor, and be atomic with respect to each other. This is clearly at odds with both
instruction reordering and data caching.
Sequential consistency inevitably prevents many architecture and compiler optimizations.
For example, the architect hastobeconservative in what can be reordered although dynamic
instruction reordering is desirable in the presence of unpredictable memory access latencies. The
compiler writer is a ected because parallel compilers often use existing sequential compilers as
a base, and sequential compilers reorder instructions based on conventional data ow analysis.
Thus, any transformation involving instruction reordering either has to be turned o , or at
least requires more sophisticated analysis [70, 109].
The desire to achieve higher performance has led to various relaxed memory models, which
can provide more implementation exibility by exposing optimizing features such as instruc-
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