Design and Verification of Adaptive Cache Coherence Protocols ...

memory regions simultaneously. In a program that assumes release consistency, for example,
the memory region used for input and output operations can have the semantics of sequential
consistency by employing an appropriate translation scheme for that region.
With both Cachet and CRF speci ed in Term Rewriting Systems, we can formally prove
that the Cachet protocol is a correct implementation of the CRF model and is free from any type
of deadlock orlivelock. The veri cation of Cachet follows the same procedure as the veri cation
of the Base, WP and Migratory protocols. To prove the soundness, for example, we de ne a
mapping function from Cachet to CRF, and show that each basic imperative rule of Cachet
can be simulated in CRF. The mapping function is based on the notion of drained terms, in
which all message queues are empty. There are many ways to drain messages from the network.
For example, we can employ backward draining for Wbb messages, and forward draining for all
other messages. The draining rules include Rules IC8-IC22, IM3-IM5, IM10-IM13, and some
additional rules that allow Wbb messages to be reclaimed at the cache sites from which they
were issued. Furthermore, we can downgrade all Migratory cells to WP cells to ensure that the
memory in a drained term always contains the most up-to-date data. This can be achieved by
including Rules IC5 and IC6 in the draining rules. The Imperative-&-Directive methodology,
together with the classi cation of basic and composite operations, has signi cantly simpli ed
the veri cation by reducing the number of rules that need to be considered.
Coarse-grain Coherence States An implementation can maintain coherence states for
cache lines rather than individual cache cells. In modern computer systems, the size of cache
lines typically ranges from 32 to 128 bytes. The state of a cache line is a concise representation
of the states of the cells in the cache line. The Clean w state, for example, means that all the
cache cells of the cache line are in the Cleanw state. When the cache line is modi ed by a
Storel instruction, the state becomes Cleanw Dirty + w ,whichimplies that at least one cache cell
of the cache line is in the Dirtyw state while all other cache cells, if any, are in the Cleanw
state. Coherence actions such as cache, writeback, downgrade and upgrade operations are all
performed at the cache line granularity. This ensures that all the cache cells in a cache line
employ the same micro-protocol at any time.
Since a cache cell can be modi ed without the exclusive ownership, there can be multiple
writers for the same cache line simultaneously. This can happen even for data-race-free programs
because of false sharing. As a result, when a cache line in the Clean w Dirty + w state is written
back to the memory, the memory should be able to distinguish between clean and dirty cells
because only the data of dirty cells can be used to update the memory. A straightforward
solution is to maintain a modi cation bit for each cache cell. At the writeback time, the
modi cation bits are also sent back so that the memory can tell which cache cells have been
modi ed. By allowing a cache line to be modi ed without the exclusive ownership, the Cachet
protocol not only reduces the latency of write operations, but also alleviates potential cache
thrashing due to false sharing.
159