Design and Verification of Adaptive Cache Coherence Protocols ...

Rule Name mem pmb mpb Next mem Next pmb Next mpb
Load-Memory mem ht,Load(a)ipmb mpb mem pmb mpbjht,mem[a]i
Store-Memory mem ht,Store(a,v)ipmb mpb mem[a:=v] pmb mpbjht,Acki
Figure 2.9: A Simple Processor-Memory Interface
Dispatch-Store Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,U)) rob2, btb, im), pmb, mpb, mem)
if Jz, U =2 rob1
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmbht,Store(a,v)i, mpb, mem)
Retire-Load Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Load(a,D),Wr(r)) rob2, btb, im), pmb, ht,vijmpb, mem)
! Sys(Proc(ia, rf , rob1 Itb(ia1,t :=v,Wr(r)) rob2, btb, im), pmb, mpb, mem)
Retire-Store Rule
Sys(Proc(ia, rf , rob1 Itb(ia1,t :=Store(a,v,D)) rob2, btb, im), pmb, ht,Ackijmpb, mem)
! Sys(Proc(ia, rf , rob1 rob2, btb, im), pmb, mpb, mem)
We de ne a simple interface between the processor and the memory that ensures memory
accesses are processed in order to guarantee sequential consistency in multiprocessor systems.
Figure 2.9 summarizes the rules for how the memory system handles memory requests from
the pmb. More aggressive implementations of memory access operations are possible, but they
often lead to various relaxed memory models in multiprocessor systems.
Load-Memory Rule
Sys(proc, ht,Load(a)ipmb, mpb, mem)
! Sys(proc, pmb, mpbjht,mem[a]i, mem)
Store-Memory Rule
Sys(proc, ht,Store(a,v)ipmb, mpb, mem)
! Sys(proc, pmb, mpbjht,Acki, mem[a:=v])
2.5 Using TRS to Prove Correctness
TRSs o er a convenient way to describe asynchronous systems and can be used to prove the
correctness of an implementation with respect to a speci cation. The correctness of an im-
plementation can be described in terms of soundness and liveness properties. A soundness
property ensures that the implementation cannot take an action that is inconsistent with the
speci cation, that is, something bad does not happen. A liveness property ensures that the
implementation makes progress eventually, that is, something good does eventually happen.
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