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4.6.2 Liveness of Base Lemma 13 ensures that whenever a processor intends to execute an instruction, the cache cell will be set to an appropriate state while the instruction remains in the processor-to-memory bu er. For a Loadl or Storel, the cache state will be set to Clean or Dirty for a Commit, the cache state will be set to Clean or Invalid for a Reconcile, the cache state will be set to Dirty or Invalid. Lemma 13 Given a Base sequence , (1) Loadl(a) 2 Pmb id( ) Loadl(a) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (2) Storel(a,-) 2 Pmb id( ) Storel(a,-) 2 Pmb id( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( )) (3) Commit(a) 2 Pmb id( ) Commit(a) 2 Pmb id ( ) ^ (Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( )) (4) Reconcile(a) 2 Pmb id( ) Reconcile(a) 2 Pmb id( ) ^ (Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( )) Proof We rst show that when a processor intends to execute an instruction, the cache cell will be brought to an appropriate state. This can be represented by the following proposition the proof follows from Lemmas 11 and 12. Loadl(a) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Storel(a,-) 2 Pmb id( ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) Commit(a) 2 Pmb id ( ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ) Reconcile(a) 2 Pmb id( ) Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) We then show that an instruction can be completed only when the address is cached in an appropriate state. This can be represented by the following proposition, which can be veri ed by simplychecking each Base rule. ht,Loadl(a)i2Pmb id( ) ^ ht,Loadl(a)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) ht,Storel(a,-)i2Pmb id( ) ^ ht,Storel(a,-)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ Cell(a,-,Dirty) 2 Cache id( ) ht,Commit(a)i2Pmb id ( ) ^ ht,Commit(a)i =2 Pmb id( ) ) Cell(a,-,Clean) 2 Cache id( ) _ a =2 Cache id( ) ht,Reconcile(a)i2Pmb id( ) ^ ht,Reconcile(a)i =2 Pmb id( ) ) Cell(a,-,Dirty) 2 Cache id( ) _ a =2 Cache id( ) This completes the proof according to Theorem-B (see Section 2.5). 2 Lemma 13 ensures that when a processor intends to execute an instruction, the cache cell will be brought into an appropriate state so that the instruction can be completed. However, this does not guarantee that the instruction will be completed since a cache state can change at any time because of voluntary rules. To ensure that each processor makes progress, an instruction must 84
e completed if it has an in nite number of opportunities to be executed. This is guaranteed by the strong fairness of Rules P1, P2, P6, P7, P11, P15, P17 and P20. Theorem 14 (Liveness of Base) Given a Base sequence , (1) ht,Loadl(-)i2Pmb id( ) ht,-i2Mpb id ( ) (2) ht,Storel(-,-)i2Pmb id( ) ht,Acki2Mpb id ( ) (3) ht,Commit(-)i2Pmb id( ) ht,Acki2Mpb id ( ) (4) ht,Reconcile(-)i2Pmb id( ) ht,Acki2Mpb id ( ) The liveness proof assumes that there can be at most one outstanding memory instruction in each processor-to-memory bu er. It is obvious that the proof still holds in the presence of multiple outstanding memory instructions, provided that the reordering mechanism ensures fair scheduling of outstanding instructions. An implementation can enforce such fairness by requiring that a stalled instruction be retried repeatedly until it is retired. 85
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73 and 74: 4.3 The Imperative Rules of the Bas
Page 75 and 76: Imperative Processor Rules Instruct
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85: eceives a CacheReq message, it will
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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