Design and Verification of Adaptive Cache Coherence Protocols ...

5.3.3 FIFO Message Passing
The liveness of WP is contingent upon FIFO message passing. Consider a scenario in which
the memory sends a Cache message to supply a data copy toacache, followed by a PurgeReq
message to request the cache copy to be purged or written back. According to Rules MC8
and MC9, the PurgeReq message would be discarded if it were received before the Cache mes-
sage, which would inevitably lead to a deadlock orlivelock situation. The minimal requirement
is that FIFO ordering must be maintained for the following messages:
FlushAck followed by Cache. The memory sends a FlushAck message to acknowledge a
writeback operation, and then sends a Cache message to supply a data copy to the cache.
Cache followed by PurgeReq. The memory sends a Cache message to a cache to supply
a data copy, and then sends a PurgeReq message to purge the data copy.
WbAck followed by PurgeReq. The memory sends a WbAck message to acknowledge
a writeback operation (the cache is allowed to retain a clean copy), and then sends a
PurgeReq message to purge the data copy.
Purge followed by CacheReq. Acache sends a Purge message to the memory after purging
a clean copy, and then sends a CacheReq message to the memory to request for a data
copy.
It is worth mentioning that FIFO message passing is not always necessary when the preced-
ing message is a directive message. For example, if a cache sends a CacheReq message followed
by a Purge message, the two messages can be received out-of-order without incurring deadlock
or livelock. In this case, the CacheReq message, which would be discarded under FIFO message
passing, invokes the memory to send a data copy to the cache. Therefore, directive messages
can be treated as low-priority messages in that they can be overtaken by imperative messages.
The WP protocol does not require FIFO ordering in the following scenarios:
CacheReq followed by Purge. Acache sends a CacheReq message to the memory. Before
the CacheReq message is received, the memory voluntarily sends a Cache message to the
cache. The cache receives the Cache message and caches the data in the Clean state.
The cache then purges the clean copy and sends a Purge message to the memory. The
CacheReq message and the Purge message can be reordered.
CacheReq followed by Wb. A cache sends a CacheReq message to the memory. Before
the CacheReq message is received, the memory voluntarily sends a Cache message to the
cache. The cache receives the Cache message and caches the data in the Clean state. The
processor performs a Storel instruction, and the cache state becomes Dirty. The cache
then sends a Wb message to write the dirty copy back to the memory. The CacheReq
message and the Wb message can be reordered.
PurgeReq followed by Cache. The memory sends a PurgeReq message to a cache, while
the address is cached in the Clean state in the cache. Before the PurgeReq message is
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