Design and Verification of Adaptive Cache Coherence Protocols ...

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Composite Imperative Rule Simulating Imperative Rules CIC1 IC4 + IC2 CIC2 IC5 + IC3 CIC3 IC6 + IC3 CIC4 IC9 + IC16 CIC5 IC10 + IC17 CIC6 IC11 + IC18 CIC7 IC12 + IC16 CIC8 IC13 + IC16 CIC9 IC22 + IC16 CIM1 IM1 + IM2 CIM2 IM9 + IM6 CIM3 IM11 + IM6 CIM4 IM12 + IM10 CIM5 IM13 + IM10 CIM6 IM15 + IM2 Figure 7.10: Simulation of Composite Imperative Rules of Cachet If a cache receives a Cachem message for an uncached address or an address cached in the CachePending state, it caches the data in the Clean state of Migratory (Rules CIC7 and CIC8). If a cache receives a WbAckm message for an address cached in the WbPending state, it sets the cache state to Clean of Migratory (Rule CIC9). Composite M-engine Rules If the memory state shows that an address is not cached in any cache, the memory can send a Cachem message to supply a Migratory copy toacache (Rule CIM1). The Cachem message behaves as a Cachew followed by anUpwm. When the memory receives a Wbw message, if the memory state shows the cache contains a WP copy for the address, the memory removes the cache identi er from the directory and suspends the writeback message (Rule CIM2). When the memory receives a Wbw message, if the memory state shows that the cache contains a Migratory copy for the address, the memory suspends the writeback message and sets the memory state to indicate that the address is no longer cached in any cache (Rule CIM3). When the memory receives a Downmb or DownVmb message, it updates the memory state to indicate that the address is no longer cached in any cache (Rules CIM4 and CIM5). When the memory state shows that an address is not residentinanycache and there is only one suspended writeback message, the memory can acknowledge the writeback message with a WbAckm message to allow thecache to retain a Migratory copy (Rule CIM6). Figure 7.10 gives the sequence of basic rules used in the simulation of a composite imperative rule. 146
7.4 The Cachet Cache Coherence Protocol In this section, we de ne the Cachet protocol that employs basic messages only. To ensure liveness, we introduce two basic directive messages, DownReqmw and DownReqwb. Whenever necessary, the memory can send a DownReqmw message to downgrade a cache cell from Mi- gratory to WP, or a DownReqwb message to downgrade a cache cell from WP to Base. Some memory states in the imperative rules need to incorporate proper information about outstand- ing directive messages in the integrated rules. The Tw[dir, ] state in the imperative rules is split into Cw[dir] and Tw[dir, ] in the integrated rules, where Tw[dir, ] implies that the memory has issued a DownReqwb message to cache sites dir. The Tm[id , ] state in the imperative rules is split into Cm[id ], T0 m [id ] and Tm[id , ] in the integrated rules, where T0 m [id ] implies that the memory has issued a DownReqmw message to cache site id , and Tm[id , ] implies that the memory has issued a DownReqmw followed by aDownReqwb to cache site id . 7.4.1 Processor Rules of Cachet Figure 7.11 gives the processor rules of Cachet. The processor rules include the imperative processor rules, and additional rules to deal with stalled instructions. All the processor rules are mandatory rules. Processor rules marked with `SF' are strongly fair. When an instruction is retired, it is removed from the processor-to-memory bu er when an instruction is stalled, it remains in the processor-to-memory bu er. For a Loadl or Storel instruction, if the address is cached in the Clean or Dirty state of any protocol, the cache supplies the accessed data or an acknowledgment to retire the instruction. If the address is uncached, the cache sends a CacheReq message to request a cache copy from the memory the instruction remains stalled until the requested data is received. For a Commit instruction, if the address is uncached or cached in the Clean state of any protocol or the Dirty state of Migratory, the cache supplies an acknowledgment to retire the instruction. If the address is cached in the Dirty state of Base, the cache sends a Wbb message to write the data back to the memory. If the address is cached in the Dirty state of WP, the cache sends a Downwb message followed by aWbb message to the memory. For a Reconcile instruction, if the address is uncached or cached in the Clean state of WP or Migratory or the Dirty state of any protocol, the cache supplies an acknowledgment to retire the instruction. If the address is cached in the Clean state of Base, the cache purges the cache cell to allow the instruction to complete. 7.4.2 Cache Engine Rules of Cachet Figure 7.12 de nes the cache engine rules of Cachet. The cache engine rules contain voluntary rules and mandatory rules. When a cache engine receives a message, it removes the message from the incoming queue. No message needs to be stalled at the cache side. The cache engine 147
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
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If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145 and 146: Invalid Commit/Reconcile Receive Ca
Page 147: Composite Imperative C-engine Rules
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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