Design and Verification of Adaptive Cache Coherence Protocols ...

for computer architecture is the development of a set of integrated design tools for modeling,
speci cation, veri cation, simulation and synthesis of computer systems.
8.1 Future Work
CRF Microprocessors We have used CRF as the speci cation for cache coherence proto-
cols. The CRF model can be implemented on most modern microprocessors via appropriate
translation schemes. However, it remains an open question how CRF instructions can be e ec-
tively incorporated into modern microprocessors. For example, what is the proper granularity
for commit, reconcile and fence instructions? What optimizations can be performed by the
compiler to eliminate unnecessary synchronizations? Since ordinary load and store instructions
are decomposed into ner-grain instructions, the instruction bandwidth needed to support a
certain level of performance is likely to be high. This can have profound impact on micro-
architectures such as instruction dispatch, cache state access and cache snoopy mechanism.
Another interesting question is the implementation of CRF instructions on architectures with
malleable caches such as column and curious caching [29].
Optimizations of Cachet The Cachet protocol can be extended in many aspects to incor-
porate more adaptivity. For example, in Cachet, an instruction is always stalled when the
cache cell is in a transient state. This constraint can be relaxed under certain circumstances:
a Loadl instruction can complete if the cache state is WbPending, and a Commit instruction
can complete if the cache state is CachePending.
The Cachet protocol uses a general cache request that draws no distinction between di erent
micro-protocols. Although a cache can indicate what copy it prefers as heuristic information,
the memory decides what copy to supply to the cache. We can extend the protocol so that
in addition to the general cache request, a cache can also send a speci c cache request for a
speci c type of cache copy. This can be useful when caches have more knowledge than the
memory about the access patterns of the program. Another advantage of having distinct cache
requests is that a cache can send a request for a WP or Migratory copy while the address is
cached in some Base state. In this case, the cache request behaves as an upgrade request from
Base to WP or Migratory.
It is worth noting that Cachet does not allow acache to request an upgrade operation from
WP to Migratory instead the cache must rst downgrade the cell from WP to Base and then
send a cache request to the memory (although the downgrade message can be piggybacked with
the cache request). We can introduce an upgrade request message so that a cache can upgrade
a WP cell to a Migratory cell without rst performing the downgrade operation (so that the
memory does not need to send the data copy tothe cache).
In Cachet, a cache can only receive a data copy from the memory, even though the most up-
to-date data resides in another cache at the time. Therefore, a Migratory copy must be written
back to the memory rst before the data can be supplied to another cache. The forwarding
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