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Design and Verification of Adaptive Cache Coherence Protocols ...

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According to Theorem-C <strong>and</strong> Lemma 45,<br />

Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a)# 2 Mout( )<br />

(Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a)# 2 Cin id( )) _<br />

Cell(a,-,C[ ]) 2 Mem( )<br />

According to Theorem-C <strong>and</strong> Lemma 46,<br />

Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a)# 2 Cin id( )<br />

(Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a) l 2 Cin id( )) _<br />

Cell(a,-,C[id ]) 2 Mem( )<br />

According to Lemmas 44, 45, <strong>and</strong> 46,<br />

Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a) l 2 Cin id( )<br />

Msg(id ,H,Purge,a) 2 MinCout id( ) _ Msg(id ,H,Flush,a,-) 2 MinCout id ( )<br />

Msg(id ,H,Purge,a) 2 Min( ) _ Msg(id ,H,Flush,a,-) 2 Min( )<br />

Msg(id ,H,Purge,a)" 2 Min( ) _ Msg(id ,H,Flush,a,-)" 2 Min( )<br />

Cell(a,-,C[ ]) 2 Mem( )<br />

Thus, Cell(a,-,T[id ]) 2 Mem( ) ^ Msg(H,id ,FlushReq,a)# 2 Mout( )<br />

Cell(a,-,C[ ]) 2 Mem( )<br />

This completes the pro<strong>of</strong> according to Theorem-A. 2<br />

The pro<strong>of</strong> above can be described in a more intuitive way. The memory sends a FlushReq<br />

message to cache site id each timeitchanges the memory state to T[id ]. When the FlushReq<br />

message is received at the cache, if the cache state is Clean or Dirty, the cache sends a Purge<br />

or Flush message to the memory otherwise the cache ignores the FlushReq message. In the<br />

latter case, if the memory state remains as T[id ], there is a Purge or Flush message in transit<br />

from the cache to the memory according to Lemma 44 (note that the memory cannot send any<br />

message to the cache while the memory state is T[id ], <strong>and</strong> FIFO message passing guarantees<br />

that any preceding message has been received before the Purge or Flush message is received).<br />

When the memory receives the Purge or Flush message, it sets the memory state to C[ ].<br />

Lemma 48 is a general form <strong>of</strong> Lemma 46. It ensures that an incoming message will eventually<br />

become a message that has no preceding message. Note that Lemma 47 ensures that a stalled<br />

<strong>Cache</strong>Req message will be processed eventually, since Rule MM1 is strongly fair.<br />

Lemma 48 Given a Migratory sequence ,<br />

(1) msg 2 Cin id( ) msg" 2 Cin id( )<br />

(2) msg 2 Min( ) msg" 2 Min( )<br />

Lemma 49 ensures that if an address is cached in the <strong>Cache</strong>Pending state, the cache state will<br />

become Clean eventually.<br />

Lemma 49 Given a Migratory sequence ,<br />

Cell(a,-,<strong>Cache</strong>Pending) 2 <strong>Cache</strong> id( ) Cell(a,-,Clean) 2 <strong>Cache</strong> id( )<br />

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