Design and Verification of Adaptive Cache Coherence Protocols ...

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Commit/Reconcile Invalid Reconcile-on-Dirty Rule Purge Loadl/Commit Storel Loadl/Storel/Reconcile Cache- Wb- Send CacheReq Pending Receive Cache Clean Receive WbAck Pending Send Wb Dirty Figure 4.3: Cache State Transitions of Base Site(id , Cell(a,v,Dirty) j cache, in, out, ht,Reconcile(a)ipmb, mpb, proc) ! Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpbjht,Acki, proc) Reconcile-on-Invalid Rule Site(id , cache, in, out, ht,Reconcile(a)ipmb, mpb, proc) if a =2 cache ! Site(id , cache, in, out, pmb, mpbjht,Acki, proc) C-engine Rules: A cache can purge a clean cell at any time.It can also write the data of a dirty cell to the memory via a writeback message (Wb), and set the cache state to WbPending, indicating that a writeback operation is being performed on the address. The cache state becomes Clean when a writeback acknowledgment (WbAck) is received. For an uncached address, a cache can send a cache request (CacheReq) to the memory to request the data, and set the cache state to CachePending, indicating that a cache copy isbeing requested on the address. When a cache message (Cache) is received, the data is written to the cache cell and the cache state becomes Clean. Figure 4.3 shows the cache state transitions. C-Purge Rule Site(id , Cell(a,-,Clean) j cache, in, out, pmb, mpb, proc) ! Site(id , cache, in, out, pmb, mpb, proc) C-Send-Wb Rule Site(id , Cell(a,v,Dirty) j cache, in, out, pmb, mpb, proc) ! Site(id , Cell(a,v,WbPending) j cache, in, out Msg(id ,H,Wb,a,v), pmb, mpb, proc) C-Send-CacheReq Rule Site(id , cache, in, out, pmb, mpb, proc) if a =2 cache ! Site(id , Cell(a,-,CachePending) j cache, in, out Msg(id ,H,CacheReq,a), pmb, mpb, proc) C-Receive-Cache Rule Site(id , Cell(a,-,CachePending) j cache, Msg(H,id ,Cache,a,v) in , out, pmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpb, proc) C-Receive-WbAck Rule Site(id , Cell(a,v,WbPending) j cache, Msg(H,id ,WbAck,a) in , out, pmb, mpb, proc) ! Site(id , Cell(a,v,Clean) j cache, in, out, pmb, mpb, proc) 72
Imperative Processor Rules Instruction Cstate Action Next Cstate Loadl(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP1 Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP2 Storel(a,v) Cell(a,-,Clean) retire Cell(a,v,Dirty) IP3 Cell(a,-,Dirty) retire Cell(a,v,Dirty) IP4 Commit(a) Cell(a,v,Clean) retire Cell(a,v,Clean) IP5 a =2 cache retire a =2 cache IP6 Reconcile(a) Cell(a,v,Dirty) retire Cell(a,v,Dirty) IP7 a =2 cache retire a =2 cache IP8 Imperative C-engine Rules Msg from H Cstate Action Next Cstate Cell(a,-,Clean) a =2 cache IC1 Cell(a,v,Dirty) hWb,a,vi!H Cell(a,v,WbPending) IC2 a =2 cache hCacheReq,ai !H Cell(a,-,CachePending) IC3 hCache,a,vi Cell(a,-,CachePending) Cell(a,v,Clean) IC4 hWbAck,ai Cell(a,v,WbPending) Cell(a,v,Clean) IC5 Imperative M-engine Rules Msg from id Mstate Action Next Mstate hCacheReq,ai Cell(a,v) hCache,a,vi!id Cell(a,v) IM1 hWb,a,vi Cell(a,-) hWbAck,ai !id Cell(a,v) IM2 Figure 4.4: Imperative Rules of Base M-engine Rules: The memory handles cache requests and writeback messages. When a cache request is received, the memory sends a cache message to supply the requested data to the requesting site. When a writeback message is received, the memory updates the memory with the committed data and sends an acknowledgment back tothecache. M-Receive-CacheReq-&-Send-Cache Rule Msite(Cell(a,v) j mem, Msg(id ,H,CacheReq,a) in , out) ! Msite(Cell(a,v) j mem, in, out Msg(H,id ,Cache,a,v)) M-Receive-Wb-&-Send-WbAck Rule Msite(Cell(a,-) j mem, Msg(id ,H,Wb,a,v) in , out) ! Msite(Cell(a,v) j mem, in, out Msg(H,id ,WbAck,a)) Figure 4.4 summarizes the imperative rules of Base. The shorthand notation `hcmd,a,vi' rep- resents a message with command cmd, address a and value v. The source and destination are implicit: for cache engine rules, an incoming message's source and destination are the memory (H) and cache id , respectively for memory engine rules, an incoming message's source and destination are cache id and the memory (H). The notation `msg ! dest' means sending the message msg to the destination dest. In the tabular description, when a processor completes or retires an instruction, the instruction is removed from the processor-to-memory bu er and the corresponding data or acknowledgment issent to the memory-to-processor bu er. Similarly, when a cache or memory engine receives and processes an incoming message, the message is consumed and removed from the incoming queue. 73
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
Page 23 and 24: that are interconnected with an o -
Page 25 and 26: although various techniques have be
Page 27 and 28: y showing that each processor can a
Page 29 and 30: s1 if p (s1) ! s2 where s1 and s2 a
Page 31 and 32: Program counter (pc) +1 Instruction
Page 33 and 34: Branch target buffer (btb) Program
Page 35 and 36: instruction is waiting to be dispat
Page 37 and 38: Current State: Proc(ia, rf , rob, b
Page 39 and 40: Rule Name mem pmb mpb Next mem Next
Page 41 and 42: Specification Implementation t 1 B
Page 43 and 44: Intuitively, \2P " means that \P is
Page 45 and 46: (a) (b) PC 1005 PC 2000 Instruction
Page 47 and 48: ewritten to s2 according to rule R.
Page 49 and 50: It can be shown that the relaxed di
Page 51 and 52: Chapter 3 The Commit-Reconcile & Fe
Page 53 and 54: Producer Storel(a,v) Commit(a) Cons
Page 55 and 56: Commit/Reconcile Purge Loadl/Commit
Page 57 and 58: instructions, because of the lack o
Page 59 and 60: CRF-Relaxed-Commit Rule Site(sache,
Page 61 and 62: 3.4 Universality of the CRF Model M
Page 63 and 64: Translation from CRF to PSO: The Fe
Page 65 and 66: proc proc proc pmb mpb pmb mpb pmb
Page 67 and 68: Chapter 4 The Base Cache Coherence
Page 69 and 70: can be classi ed into two non-overl
Page 71 and 72: arbitrarily in an outgoing queue (t
Page 73: 4.3 The Imperative Rules of the Bas
Page 77 and 78: Figure 4.5 de nes the rules of the
Page 79 and 80: 4.5.2 Mapping from Base to CRF We d
Page 81 and 82: Base Imperative Rule CRF Rule IP1 (
Page 83 and 84: Base Rule Base Imperative Rule P1 I
Page 85 and 86: eceives a CacheReq message, it will
Page 87 and 88: e completed if it has an in nite nu
Page 89 and 90: SYS Sys(MSITE, SITEs) System MSITE
Page 91 and 92: Commit/Reconcile C-Receive-WbAck Ru
Page 93 and 94: message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
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Lemma 38 D is strongly terminating
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Migratory Imperative Rule CRF Rules
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Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
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According to Theorem-C and Lemma 45
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CacheReq message. In the latter cas
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Chapter 7 Cachet: A Seamless Integr
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7.1.1 Putting Things Together It is
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Writeback Operations In Cachet, a w
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Composite Message Equivalent Sequen
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Imperative Processor Rules Instruct
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Invalid Commit/Reconcile Receive Ca
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Composite Imperative C-engine Rules
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7.4 The Cachet Cache Coherence Prot
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Voluntary C-engine Rules Cstate Act
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The memory processes an incoming Ca
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The inaccuracy of memory states can
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C-engine Rule of Cachet Deriving Im
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Composite Mandatory Processor Rules
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memory regions simultaneously. In a
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Chapter 8 Conclusions This thesis h
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and heuristic policies. Mandatory r
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technique can be used to allow a ca
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Voluntary C-engine Rules Cstate Act
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FIFO Message Passing msg1 msg2 msg2
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[13] J. K. Archibald. The Cache Coh
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[41] A. Erlichson, N. Nuckolls, G.
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[71] J. Kuskin, D. Ofelt, M. Heinri
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[101] F. Pong and M. Dubois. A New
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