Design and Verification of Adaptive Cache Coherence Protocols ...

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Imperative M-engine Rules Msg from id Mstate Action Next Mstate Cell(a,v,Tw[dir, ]) (id =2 dir) hCachew,a,vi!id Cell(a,v,Tw[id jdir, ]) IM1 Cell(a,v,Tw[id , ]) hUpwm,ai!id Cell(a,v,Tm[id , ]) IM2 hCacheReq,ai Cell(a,v,Tw[dir,sm]) (id =2 dir) hCacheb,a,vi!id Cell(a,v,Tw[dir,sm]) IM3 Cell(a,v,Tw[dir,sm]) (id 2 dir) Cell(a,v,Tw[dir,sm]) IM4 Cell(a,v,Tm[id ,sm]) Cell(a,v,Tm[id ,sm]) IM5 hWbb,a,vi Cell(a,v1,Tw[dir,sm]) (id =2 dir) Cell(a,v1,Tw[dir,(id ,v)jsm]) IM6 Cell(a,v1,Tw[id jdir,sm]) Cell(a,v1,Tw[dir,(id ,v)jsm]) IM7 Cell(a,v1,Tm[id1,sm]) (id 6= id1) Cell(a,v1,Tm[id1,(id ,v)jsm]) IM8 Cell(a,v1,Tm[id ,sm]) Cell(a,v1,Tw[ ,(id ,v)jsm]) IM9 hDownwb,ai Cell(a,v,Tw[id jdir,sm]) Cell(a,v,Tw[dir,sm]) IM10 Cell(a,v,Tm[id ,sm]) Cell(a,v,Tw[ ,sm]) IM11 hDownmw,ai Cell(a,v,Tm[id ,sm]) Cell(a,v,Tw[id ,sm]) IM12 hDownVmw,a,vi Cell(a,-,Tm[id ,sm]) Cell(a,v,Tw[id ,sm]) IM13 Cell(a,-,Tw[ ,(id ,v)jsm]) hWbAckb,ai!id Cell(a,v,Tw[ ,sm]) IM14 Cell(a,-,Tw[ ,(id ,v)]) hWbAckw,ai!id Cell(a,v,Tw[id , ]) IM15 Figure 7.8: Imperative Memory Engine Rules of Cachet When the memory receives a Wbb message, if the memory state shows that the cache contains a Migratory copy for the address, the memory suspends the writeback message and sets the memory state to indicate that the address is no longer cached in any cache (Rule IM9). This can happen if the memory sends a Cachew message followed by an Upwm message to the cache before it receives the Wbb message. The Cachew and Upwm messages will be discarded at the cache (Rules IC11 and IC18). When the memory receives a Downwb message, if the memory state shows that the cache contains a WP cell for the address, the memory removes the cache identi er from the directory (Rule IM10). When the memory receives a Downwb message, if the memory state shows that the cache contains a Migratory cell for the address, the memory sets the memory state to indicate that the address is no longer cached in any cache (Rule IM11). This can happen when the memory sends an Upwm message to the cache before it receives the Downwb message. The Upwm message will be discarded at the cache (Rules IC14, IC15, IC18, IC19 and IC20). When the memory receives a Downmw or DownVmw message, it sets the memory state accordingly to indicate that the cache cell has been downgraded to WP (Rules IM12 and IM13). When the memory state shows that an address is not resident inanycache, the memory can resume suspended writeback messages. For each writeback message, the memory updates the memory cell and acknowledges the cache via a WbAckb message (Rule IM14). The last resumed message can be acknowledged with a WbAckw message so that the cache can retain a WP copy (Rule IM15). There are some subtle issues that must be handled properly to ensure correctness. As in Base, the memory cannot send a Cacheb message to a cache without a CacheReq message from the cache site. As in WP, the memory cannot be updated if the directory shows that the address is cached under WP in some caches. Since the memory maintains no information about Base 144
Composite Imperative C-engine Rules Msg from H Cstate Action Next Cstate Cell(a,v,Dirtyw) hWbw,a,vi!H Cell(a,v,WbPending) CIC1 Cell(a,v,Cleanm) hDownmb,ai!H Cell(a,v,Cleanb) CIC2 Cell(a,v,Dirtym) hDownVmb,a,vi!H Cell(a,v,Cleanb) CIC3 hCachem,a,vi Cell(a,-,Cleanb) Cell(a,v,Cleanm) CIC4 Cell(a,v1,Dirtyb) Cell(a,v1,Dirtym) CIC5 Cell(a,v1,WbPending) Cell(a,v1,WbPending) CIC6 Cell(a,-,CachePending) Cell(a,v,Cleanm) CIC7 a =2 cache Cell(a,v,Cleanm) CIC8 hWbAckm,ai Cell(a,v,WbPending) Cell(a,v,Cleanm) CIC9 Composite Imperative M-engine Rules Msg from id Mstate Action Next Mstate Cell(a,v,Tw[ , ]) hCachem,a,vi!id Cell(a,v,Tm[id , ]) CIM1 hWbw,a,vi Cell(a,v1,Tw[id jdir,sm]) Cell(a,v1,Tw[dir,(id ,v)jsm]) CIM2 Cell(a,v1,Tm[id ,sm]) Cell(a,v1,Tw[ ,(id ,v)jsm]) CIM3 hDownmb,ai Cell(a,v,Tm[id ,sm]) Cell(a,v,Tw[ ,sm]) CIM4 hDownVmb,a,vi Cell(a,-,Tm[id ,sm]) Cell(a,v,Tw[ ,sm]) CIM5 Cell(a,-,Tw[ ,(id ,v)]) hWbAckm,ai!id Cell(a,v,Tm[id , ]) CIM6 Figure 7.9: Composite Imperative Rules of Cachet cells, it may receive a writeback message from a cache although the memory state shows that the address is not resident in the cache. A writeback operation cannot be acknowledged before all WP and Migratory cells of the address have been purged or downgraded to Base cells. 7.3.4 Composite Imperative Rules Figure 7.9 de nes some composite imperative rules of Cachet. A composite imperative rule can be simulated by basic imperative rules, and therefore cannot compromise the soundness of the protocol. Composite C-engine Rules A cache can write the dirty data of a WP cell back to the memory via a Wbw message and set the cache state to WbPending (Rule CIC1). The Wbw message behaves as a Downwb followed by aWbb. Acache can downgrade a cache cell from Migratory to Base, and inform the memory via aDownmb or DownVmb message (Rules CIC2 and CIC3). The Downmb message behaves as a Downmw followed by aDownwb, and the DownVmb message behaves as a DownVmw followed by aDownwb. If a cache receives a Cachem message for a clean Base cell, it purges the cache cell and caches the data in the Clean state of Migratory (Rules CIC4). If a cache receives a Cachem message for a dirty Base cell, it upgrades the cache cell to Migratory (Rule CIC5). If a cache receives a Cachem message for an address cached in the WbPending state, it discards the message (Rule CIC6). 145
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CSAIL Computer Science and Artifici
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Design and Veri cation of Adaptive
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I am truly grateful to my parents f
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4 The Base Cache Coherence Protocol
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List of Figures 1.1 Impact of Archi
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Chapter 1 Introduction Shared memor
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transparent and exposed only for lo
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Example 1: Can both registers r1 an
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and release locks, which guard ever
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that are interconnected with an o -
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although various techniques have be
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y showing that each processor can a
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s1 if p (s1) ! s2 where s1 and s2 a
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Program counter (pc) +1 Instruction
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Branch target buffer (btb) Program
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instruction is waiting to be dispat
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Current State: Proc(ia, rf , rob, b
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Rule Name mem pmb mpb Next mem Next
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Specification Implementation t 1 B
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Intuitively, \2P " means that \P is
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(a) (b) PC 1005 PC 2000 Instruction
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ewritten to s2 according to rule R.
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It can be shown that the relaxed di
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Chapter 3 The Commit-Reconcile & Fe
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Producer Storel(a,v) Commit(a) Cons
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Commit/Reconcile Purge Loadl/Commit
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instructions, because of the lack o
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CRF-Relaxed-Commit Rule Site(sache,
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3.4 Universality of the CRF Model M
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Translation from CRF to PSO: The Fe
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proc proc proc pmb mpb pmb mpb pmb
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Chapter 4 The Base Cache Coherence
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can be classi ed into two non-overl
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arbitrarily in an outgoing queue (t
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4.3 The Imperative Rules of the Bas
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Imperative Processor Rules Instruct
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Figure 4.5 de nes the rules of the
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4.5.2 Mapping from Base to CRF We d
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Base Imperative Rule CRF Rule IP1 (
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Base Rule Base Imperative Rule P1 I
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eceives a CacheReq message, it will
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e completed if it has an in nite nu
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SYS Sys(MSITE, SITEs) System MSITE
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Commit/Reconcile C-Receive-WbAck Ru
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message can be resumed eventually.
Page 95 and 96: If the memory state shows that the
Page 97 and 98: 5.3.3 FIFO Message Passing The live
Page 99 and 100: Figure 5.7 gives the M-engine rules
Page 101 and 102: Backward-Message-Cache-to-Mem-for-W
Page 103 and 104: 5.4.3 Simulation of WP in CRF Theor
Page 105 and 106: WP Imperative Rule CRF Rules IP1 (L
Page 107 and 108: WP Rule WP Imperative & Directive R
Page 109 and 110: (4) Msg(H,id ,Cache,a,-)" 2 Cin id(
Page 111 and 112: This completes the proof according
Page 113 and 114: emains as CachePending, there mustb
Page 115 and 116: M-engine Rules Msg from id Mstate A
Page 117 and 118: Chapter 6 The Migratory Cache Coher
Page 119 and 120: Commit/Reconcile Send Purge Loadl/C
Page 121 and 122: Mandatory Processor Rules Instructi
Page 123 and 124: while the memory sends a FlushReq m
Page 125 and 126: Lemma 38 D is strongly terminating
Page 127 and 128: Migratory Imperative Rule CRF Rules
Page 129 and 130: Cell(a,v,C[id ]) 2 Mem(s) _ Cell(a,
Page 131 and 132: According to Theorem-C and Lemma 45
Page 133 and 134: CacheReq message. In the latter cas
Page 135 and 136: Chapter 7 Cachet: A Seamless Integr
Page 137 and 138: 7.1.1 Putting Things Together It is
Page 139 and 140: Writeback Operations In Cachet, a w
Page 141 and 142: Composite Message Equivalent Sequen
Page 143 and 144: Imperative Processor Rules Instruct
Page 145: Invalid Commit/Reconcile Receive Ca
Page 149 and 150: 7.4 The Cachet Cache Coherence Prot
Page 151 and 152: Voluntary C-engine Rules Cstate Act
Page 153 and 154: The memory processes an incoming Ca
Page 155 and 156: The inaccuracy of memory states can
Page 157 and 158: C-engine Rule of Cachet Deriving Im
Page 159 and 160: Composite Mandatory Processor Rules
Page 161 and 162: memory regions simultaneously. In a
Page 163 and 164: Chapter 8 Conclusions This thesis h
Page 165 and 166: and heuristic policies. Mandatory r
Page 167 and 168: technique can be used to allow a ca
Page 169 and 170: Voluntary C-engine Rules Cstate Act
Page 171 and 172: FIFO Message Passing msg1 msg2 msg2
Page 173 and 174: [13] J. K. Archibald. The Cache Coh
Page 175 and 176: [41] A. Erlichson, N. Nuckolls, G.
Page 177 and 178: [71] J. Kuskin, D. Ofelt, M. Heinri
Page 179 and 180: [101] F. Pong and M. Dubois. A New
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